CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 139

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.4
16.4.1
A Power on Reset (POR) is triggered whenever the supply
voltage is below the POR trip point. POR ends once the sup-
ply voltage rises above this voltage. Refer to the
LVD chapter on page 143
tion of the POR block.
POR consists of two pieces: an Imprecise POR (IPOR) and
a Precision POR (PPOR). “POR” refers to the OR of these
two functions. IPOR has coarser accuracy and its trip point
is typically lower than PPOR’s trip point. PPOR is derived
from a circuit that is calibrated (during boot) for a very accu-
rate location of the POR trip point.
During POR (POR=1), the IMO is powered off for low power
during startup. After POR deasserts, the IMO is started (see
Figure
POR configures register reset status bits as shown in
Reset Details on page
16.4.2
An External Reset (XRES) is caused by pulling the XRES
pin high. The XRES pin has an always-on, pull down resis-
tor, so it does not require an external pull down for operation
and can be tied directly to ground or left open. Behavior after
XRES is similar to POR.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
16-4).
Timing Diagrams
Power On Reset
External Reset
IMO (not to scale)
IMO (not to scale)
141.
for more information on the opera-
Sleep Timer
Sleep Timer
WDR: Reset 1 cycle, then one additional cycle before the CPU reset is released.
IRES: Reset 1 cycle, then 2048 additional cycles low power hold-off, and then 1
cycle with IMO on before the CPU reset is released.
CPU Reset
CPU Reset
IMO PD
IMO PD
CLK32
CLK32
Reset
Reset
(Stays low)
Figure 16-3. Key Signals During WDR
0
0
POR and
16.4.4
During XRES (XRES=1), the IMO is powered off for low
power during startup. After XRES deasserts, the IMO is
started (see
How the XRES configures register reset status bits is shown
in
16.4.3
The user has the option to enable the Watchdog Timer
Reset (WDR), by clearing the PORS bit in the CPU_SCR0
register. After the PORS bit is cleared, the watchdog timer
cannot be disabled. The only exception to this is if a POR/
XRES event takes place, which disables the WDR. Note that
a WDR does not clear the watchdog timer. See
Timer on page 81
When the watchdog timer expires, a watchdog event occurs,
resulting in the reset sequence. Some characteristics
unique to the WDR are as follows.
■
■
■
How the WDR configures register reset status bits is shown
in
1
1
16.4.4 Reset Details on page
16.4.4 Reset Details on page
PSoC device reset asserts for one cycle of the CLK32K
clock (at its reset state).
The IMO is not halted during or after WDR (that is, the
part does not go through a low power phase).
CPU operation re-starts one CLK32K cycle after the
internal reset deasserts (see
2
2
Figure
Watchdog Timer Reset
N=2048
for details of the watchdog operation.
16-4).
141.
141.
Figure
16-3).
System Resets
Watchdog
139
[+] Feedback