CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 180

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.3.13
The PSoC Memory Arbiter Read Address Register
(PMAx_RA) is used to set the beginning address for the
PMA channel. A PMAx_RA register address uses the same
physical register as the PMAx_WA register address. There-
fore, when the read address is changed, the write address is
also changed and the PMAx_WA and PMAx_RA registers
always return the same value when read. When a
PMAx_RA register is written, the address is stored and the
value of the corresponding SRAM address is loaded into the
channel's PMAx_DR. Therefore, this register must only be
written after valid data has been stored in SRAM for the
channel.
20.3.14
The USB Control Register 1 (USB_CR1) is used to config-
ure the internal regulator and the oscillator tuning capability.
Bit 2: BusActivity. The BusActivity bit is a "sticky" bit that
detects any non-idle USB event that has occurred on the
USB bus. After set to high by the SIE to indicate the bus
activity, this bit retains its logical high value until firmware
clears it. Writing a '0' to this bit clears it; writing a '1' pre-
serves its value. ‘0‘ is no activity. '1' is non-idle activity (D+ =
low) was detected since the last time the bit was cleared.
Full-Speed USB
180
1,3Ch
1,3Dh
1,3Eh
1,3Fh
1,40h
1,41h
1,42h
1,43h
1,4Ch
1,4Dh
1,4Eh
1,4Fh
1,50h
1,51h
1,52h
1,53h
1,30h
Address
Address
PMA0_RA
PMA1_RA
PMA2_RA
PMA3_RA
PMA4_RA
PMA5_RA
PMA6_RA
PMA7_RA
PMA8_RA
PMA9_RA
PMA10_RA
PMA11_RA
PMA12_RA
PMA13_RA
PMA14_RA
PMA15_RA
USB_CR1
PMAx_RA Register
USB_CR1 Register
Name
Name
Bit 7
Bit 7
Bit 6
Bit 6
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Bit 5
Bit 5
Bit 4
Bit 4
Read Address[7:0]
Read Address[7:0]
Read Address[7:0]
Read Address[7:0]
Read Address[7:0]
Read Address[7:0]
Read Address[7:0]
Read Address[7:0]
Read Address[7:0]
Read Address[7:0]
Read Address[7:0]
Read Address[7:0]
Read Address[7:0]
Read Address[7:0]
Read Address[7:0]
Read Address[7:0]
Bits 7 to 0: Address[7:0]. The value returned when this
register is read depends on whether the PMA channel is
being used by the USB SIE or by the M8C. In the USB SIE
case, this register always returns the beginning SRAM
address for the PMA channel. In the M8C case, this register
always returns the next SRAM address that is used by the
PMA channel, if a byte is read from the channel's data regis-
ter (PMAx_DR) by the M8C.
For additional information, refer to the
page
Bit 1: EnableLock. Set this bit to turn on the automatic fre-
quency locking of the internal oscillator to USB traffic.
Unless an external clock is being provided, this bit must
remain set for proper USB operation. ‘0‘ is locking disabled.
'1' is locking enabled.
Bit 0: RegEnable. This bit controls the operation of the
internal USB regulator. For applications with device supply
voltages in the 5V range, set this bit high to enable the inter-
nal regulator. For device supply voltages in the 3.3V range,
clear this bit to connect the transceiver directly to the supply.
‘0‘ is passthrough mode. Use for Vdd = 3.3V range. '1' is
regulating mode. Use for Vdd = 5V range.
For additional information, refer to the
page
264.
262.
Bit 3
Bit 3
BusActivity
Bit 2
Bit 2
EnableLock
Bit 1
Bit 1
PMAx_RA register on
USB_CR1 register on
RegEnable
Bit 0
Bit 0
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
Access
Access
# : 0
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