CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 217

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.3.29 CS_STAT
This register controls the TrueTouch counter options.
Never modify the interrupt mask bits while the block is enabled. If a modification to bits 3 to 0 is necessary while the block is
enabled, then pay close attention to ensure that the status bits 7 to 4, are not accidentally cleared. You do this by writing a ‘1’
to all of the status bits when writing to the mask bits. For additional information, refer to the
the TrueTouch Module chapter .
Bit
7
6
5
4
3
2
1
0
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Individual Register Names and Addresses:
CS_STA
T
Access : POR
Bit Name
INS
COLS
COHS
PPS
INM
COLM
COHM
PPM
Name
: 0,A6h
TrueTouch Status Register
RC : 0
INS
7
RC : 0
COLS
6
Description
Input Status.
0
1
Counter Carry Out Low Status.
0
1
Counter Carry Out High Status.
0
1
Pulse Width/Period Measurement Status.
0
1
Input Interrupt/Mask.
0
1
Counter Carry Out Low Interrupt Mask.
0
1
Counter Carry Out High Interrupt Mask.
0
1
Pulse Width/Period Measurement Interrupt Mask.
0
1
No event detected.
A rising edge on the selected input was detected. Cleared by writing a ‘0’ to this bit.
No event detected.
A carry out from low byte counter was detected. Cleared by writing a ‘0’ back to this bit.
No event detected.
A carry out from high byte counter was detected. Cleared by writing a ‘0’ back to this bit.
No event detected.
A pulse width or period measurement was completed. Cleared by writing a ‘0’ back to this
bit.
Disabled.
Input event is enabled to assert the block interrupt.
Disabled.
Counter carry out low is enabled to assert the block interrupt.
Disabled.
Counter carry out high is enabled to assert the block interrupt.
Disabled.
Completion of a pulse width or period measurement is enabled to assert the block interrupt.
RC : 0
COHS
5
RC : 0
PPS
4
RW : 0
INM
3
RW : 0
COLM
2
Register Definitions on page 92
RW : 0
COHM
1
0,A6h
RW : 0
CS_STAT
0,A6h
PPM
0
217
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