CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 254

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CPU_F
21.3.63 CPU_F
This register provides read access to the M8C flags.
The AND f, expr; OR f, expr; and XOR f, expr flag instructions are used to modify this register. In the table above, note that the
reserved bit is a grayed table cell and is not described in the bit description section below. Reserved bits must always be writ-
ten with a value of ‘0’. For additional information, refer to the
ister Definitions on page 48
Bit
7:6
5
4
2
(continued on next page)
254
Individual Register Names and Addresses:
CPU_F : x,F7h
Access : POR
Bit Name
x,F7h
PgMode[1:0]
BINC
XIO
Carry
Name
M8C Flag Register
7
PgMode[1:0]
RL : 0
in the Interrupt Controller chapter.
6
Description
00b
01b
10b
11b
Bit Implemented Not Connected.
0
1
Set by the M8C CPU Core to indicate whether there has been a carry in the previous logical/arith-
metic operation.
0
1
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Direct Address mode and Indexed Address mode operands are referred to RAM Page 0,
regardless of the values of CUR_PP and IDX_PP. Note that this condition prevails upon
entry to an Interrupt Service Routine when the CPU_F register is cleared.
Direct Address mode instructions are referred to Page 0.
Indexed Address mode instructions are referred to the RAM page specified by the stack
page pointer, STK_PP.
page pointer, CUR_PP.
Indexed Address mode instructions are referred to the RAM page specified by the index
page pointer, IDX_PP.
page pointer, CUR_PP.
Indexed Address mode instructions are referred to the RAM page specified by the stack
page pointer, STK_PP.
Normal register address space.
Extended register address space. Primarily used for configuration.
No carry.
Carry.
Direct Address mode instructions are referred to the RAM page specified by the current
Direct Address mode instructions are referred to the RAM page specified by the current
RL : 0
BINC
5
RL : 0
Register Definitions on page 32
XIO
4
3
RL : 0
Carry
2
in the M8C chapter and the
x,F7h
RL : 0
Zero
1
RL : 0
GIE
0
Reg-
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