CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 61

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.4
The Input/Output Configuration Register 1 (IO_CFG1) con-
figures the Port 1 output regulator and set the Interrupt
mode for all GPIO.
Bit 7: StrongP. Setting this bit increases the drive strength
and edge ratio for high outputs.
Bit 5 and 4: Range[1:0]. These bits select the regulator
output level for Port 1. Available levels are 3.0V, 1.8V, and
2.5V.
Selects the high output level for Port 1 outputs.
6.2.5
The Input/Output Configuration Register 2 (IO_CFG2)
selects output regulated supply and clock rates.
Bits 5 to 3: REG_LEVEL[2:0]. These bits select output
regulated supply.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
1,DCh
00
01
10
11
1,DEh
000
001
010
011
100
101
110
111
Address
Address
REG_LEVEL[2:0]
Range[1:0]
IO_CFG1
IO_CFG2
IO_CFG1 Register
IO_CFG2 Register
Name
Name
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
StrongP
Bit 7
Bit 7
3.0 volts
3.0 volts
1.8 volts
2.5 volts
Approx. Regulated Supply (V)
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
Bit 6
Bit 6
Output Level
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
Bit 5
Bit 5
Range[1:0]
REG_LEVEL[2:0]
Bit 4
Bit 4
Bit 3 P1_LOW_THRS. This bit reduces the threshold volt-
age of the P1 port input buffers so that there are no compat-
ibility issues when Port 1 is communicating at regulated
voltage levels.
‘0’ is standard threshold of VIH, VIL. ‘1’ is reduce threshold
of VIH, VIL.
Bit 2: SPICLK_ON_P10. When this bit is set to ‘1’, the SPI
clock is mapped to Port 1 pin 0. Otherwise, it is mapped to
Port 1 pin 3.
Bit 1: REG_EN. The Register Enable bit (REG_EN) con-
trols the regulator on Port 1 outputs.
Bit 0: IO INT. This bit sets the GPIO Interrupt mode for all
pins in the CY8CTMG20x, CY8CTST200 PSoC devices.
GPIO interrupts are controlled at each pin by the PRTxIE
registers, and also by the global GPIO bit in the INT_MSK0
register.
For additional information, refer to the
page
Bits 1 to 0: REG_CLOCK[1:0]. The Regulated I/O charge
pump can operate with a maximum clock speed of 12 MHZ.
The REG_CLOCK[1:0] bits select clocking options for the
regulator. Setting REG_CLOCK[1:0] to ‘10’ should be used
with 24 MHz SYSCLK and ‘01’ should be used with 6/12
MHz SYSCLK.
For additional information, refer to the
page
10
01
P1_LOW_
THRS
272.
275.
REG_CLOCK[1:0]
Bit 3
Bit 3
SPICLK_
ON_P10
Bit 2
Bit 2
24 MHz
6/12 MHz
REG_EN
Bit 1
REG_CLOCK[1:0]
Bit 1
General Purpose I/O (GPIO)
SYSCLK Clock Rate
IO_CFG1 register on
IO_CFG2 register on
Bit 0
IOINT
Bit 0
RW : 00
Access
Access
RW : 00
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