CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 114

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

view on page 70
ECO.
Bit 6: Disable Buzz. Setting this bit high causes the band-
gap and POR/LVD systems to remain powered off continu-
ously during sleep. In this case, there is no periodic “buzz”
(brief wakeup) of these functions during sleep. This bit has
no effect when the No Buzz bit is set high.
Bit 5: No Buzz. Normally, when the SLEEP bit is set in the
CPU_SCR register, all PSoCdevice systems are powered
down, including the bandgap reference. However, to facili-
tate the detection of POR and LVD events at a rate higher
than the sleep interval, the bandgap circuit is powered up
periodically (for about 60 μ s) at the Sleep System Duty
Cycle, which is independent of the sleep interval and typi-
cally higher. When the No Buzz bit is set, the Sleep System
Duty Cycle value is overwritten and the bandgap circuit is
forced to be on during sleep. This results in faster response
to an LVD or POR event (continuous detection as opposed
to periodic), at the expense of higher average sleep current.
Bits 4 and 3: Sleep[1:0]. The
selections are shown in the table below. Sleep intervals are
approximate based upon the accuracy of the internal low
speed oscillator.
Bits 2 to 0: CPU Speed[2:0]. The M8C operates over a
range of CPU clock speeds, allowing you to tailor the M8C’s
performance and power requirements to the application.
The reset value for the CPU speed bits is 010b. Therefore,
the default CPU speed is one-half of the clock source. The
internal main oscillator is the default clock source for the
CPU speed circuit; therefore, the default CPU speed is 6.0
MHz. See
on the supported frequencies for externally supplied clocks.
The CPU frequency is changed with a write to the
OSC_CR0 register. There are eight frequencies generated
from a power-of-two divide circuit that is selected by a 3-bit
code. At any given time, the CPU 8-to-1 clock mux is select-
ing one of the available frequencies, which is resynchro-
nized to the 24 MHz master clock at the output. The IMO
frequency is also selectable, as discussed in the IMO chap-
ter in the
an option to lower both system and CPU clock speed to
Digital Clocks
114
00b (Default)
01b
10b
11b
Sleep Interval
OSC_CR[4:3]
Architectural Description on page
External Clock on page 110
512
4096
32,768
64
Sleep Timer
for the proper sequence to enable the
Clocks
1.95 ms
15.6 ms
125 ms
1 sec
Sleep Period
(Nominal)
available
for more information
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
6 ms
47 ms
375 ms
3 sec
Watchdog Period
sleep
63. This offers
(Nominal)
interval
save power. The selections are shown in the table below
(reset state is 001b).
An automatic protection mechanism is available for systems
that need to run at peak CPU clock speed but cannot guar-
antee a high enough supply voltage for that clock speed.
See the LVDTBEN bit in the
page 144
Note During USB operation, the CPU speed can be set to
any setting. Be aware that USB throughput decreases with a
decrease in CPU speed. For maximum throughput, the CPU
clock should be made equal to the system clock. The sys-
tem clock must be 24 MHz for USB operation.
For additional information, refer to the
page
000b
001b
010b
011b
100b
101b
110b
111b
Bits
276.
750 kHz
1.5 MHz
3 MHz
6 MHz
375 kHz
187.5 kHz
46.8 kHz
23.4 kHz
Internal Main
Oscillator
for more information.
6 MHz
Internal Main
1.5 MHz
3.0 MHz
6.0 MHz
12.0 MHz
750 Hz
375 kHz
93.7 kHz
46.8 kHz
Oscillator
12 MHz
3 MHz
6 MHz
12 MHz
24 MHz
1.5 MHz
750 kHz
187.5 kHz
93.7 kHz
Internal Main
Oscillator
24 MHz
VLT_CMP Register on
OSC_CR0 register on
EXTCLK/ 8
EXTCLK/ 4
EXTCLK/ 2
EXTCLK/ 1
EXTCLK/ 16
EXTCLK/ 32
EXTCLK/ 128
EXTCLK/ 256
External Clock
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