CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 125

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.3.8
The I
write interface to the data buffer. Whenever this register is
read, the data at the location pointed to by the CPU current
pointer (CPU_CP) is returned. Similarly, whenever this reg-
ister is written, the data is transferred to the buffer and writ-
ten at the location pointed to by the CPU current pointer
(CPU_CP). Whenever this register is read, without initializ-
ing the RAM contents either through the I
face, no valid value is returned.
The M8C accesses the data buffer through this register
interface (I2C_BUF). Since the M8C issues an I/O read sig-
nal before an I/O write for some opcodes, the pointers
(CPU_CP) to the data buffer increment unnecessarily
because of an extra I/O read before an I/O write. Hence, all
the I/O reads that occur in FIRST phase are ignored. The I/
O reads that occur only in EXEC phase are taken as actual
I/O reads for this register.
So, only the following basic M8C register access instruc-
tions may be used for accessing this register:
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
0,CFh
Address
2
C Data Buffer Register (I2C_BUF) is the CPU read/
I2C_BUF
I2C_BUF Register
Name
Bit 7
Bit 6
2
C or CPU inter-
Bit 5
Bit 4
Data Buffer[7:0]
MOV A, reg[expr]
MOV A, reg[X+expr]
MOV [expr], [expr]
MOV reg[expr], A
MOV reg[X+expr], A
MOV reg[expr], expr
MOV reg[X+expr], expr
Note When in compatibility mode, this register is not in use.
Bits 7 to 0: Data Buffer[7:0]. The I
ter (I2C_BUF) is the CPU read/write interface to the data
buffer. Whenever this register is read, the data at the loca-
tion pointed to by the CPU current pointer (CPU_CP) is
returned. Similarly, whenever this register is written, the
data is transferred to the buffer and written at the location
pointed to by the CPU current pointer (CPU_CP). Whenever
this register is read, without initializing the RAM contents
either through the I
returned.
For additional information, refer to the
page
233.
Bit 3
Bit 2
2
C or CPU interface, no valid value is
Bit 1
2
C Data Buffer Regis-
I2C_BUF register on
Bit 0
I2C Slave
RW : 00
Access
125
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