CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 123

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.3.2
The I
enhanced feature status. All bits are read only. When the
bits of I2C_XCFG are left in their reset state, the block is in
compatibility mode, and this register is not in use.
Bit 1: Dir. This bit indicates the direction of the current
transfer. A ‘1’ indicates a master read, and a ‘0’ indicates a
master write. It is only valid when the Slave Busy bit (bit 0) is
set to ‘1’.
15.3.3
The I
slave’s 7-bit address. All bits are RW.
Note When hardware address compare mode is not
enabled in the I2C_XCFG register, this register is not in use.
15.3.4
The I
the base address value of the RAM data buffer.
Note When in compatibility mode, this register is not in use.
Bits 4 to 0: I2C Base Pointer[4:0]. In the EZI2C protocol,
the first data byte after the slave address transaction in write
mode is the base address for subsequent reads and writes
and it is transferred directly into this register. If the desired
transaction is a master write to the slave, subsequent bytes
are written to the RAM buffer starting with this address and
auto incremented (see
In case of a read, a Start or Restart must be issued and the
read location starts with this address and again subsequent
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
0,C9h
0,CAh
0,CBh
Address
Address
Address
2
2
2
C Base Address Pointer Register (I2C_BP) contains
C Slave Address Register (I2C_ADDR) holds the
C Extended Status Register (I2C_XSTAT) reads
I2C_XSTAT
I2C_ADDR
I2C_BP
I2C_XSTAT Register
I2C_ADDR Register
I2C_BP Register
Name
Name
Name
I2C_CP
Bit 7
Bit 7
Bit 7
Register).
Bit 6
Bit 6
Bit 6
Bit 5
Bit 5
Bit 5
Bit 4
Bit 4
Bit 4
Bits 0: Slave Busy. This bit is set upon a hardware
address compare and is reset upon the following stop sig-
nal. Poll this bit to determine when the slave is busy and the
buffer module is being accessed.
For additional information, refer to the
on page
Bits 6 to 0: Slave Address[6:0] . These 7 bits hold the
slave’s own device address.
For additional information, refer to the
on page
read addresses are auto incremented as pointed to by the
I2C_CP register value. The value of this register is modified
only at the beginning of every I
master must always supply a value for this register in the
first byte of data after the slave’s address in a given write
transaction. If performing reads, the master need not set the
value of this register. The current value of this register is
also used directly for reads.
For additional information, refer to the
page
Slave Address[6:0]
229.
Bit 3
Bit 3
Bit 3
227.
228.
I2C Base Pointer[4:0]
Bit 2
Bit 2
Bit 2
Bit 1
Bit 1
Bit 1
Dir
2
C write transaction. The I
Slave Busy
I2C_XSTAT register
I2C_BP register on
I2C_ADDR register
Bit 0
Bit 0
Bit 0
I2C Slave
RW : 00
Access
Access
Access
R : 00
R : 0
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