CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 276

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OSC_CR0
21.4.17 OSC_CR0
This register is used to configure various features of internal clock sources and clock nets.
In the table above, note that the reserved bit is a grayed table cell and is not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
page 112
Bit
7
6
5
4:3
2:0
276
Individual Register Names and Addresses:
OSC_CR0: 1,E0h
Access : POR
Bit Name
1,E0h
X32ON
Disable Buzz
No Buzz
Sleep[1:0]
CPU Speed[2:0]
Name
in the Digital Clocks chapter.
Oscillator Control Register 0
X32ON
RW: 0
7
Disable Buzz
RW : 0
6
Description
Select bit for the external 32 kHz external crystal oscillator (ECO). See the
page 70
0
1
Option to disable buzz during sleep. This bit has lower priority than the No Buzz bit. Therefore, if No
Buzz = 1, the Disable Buzz bit has no effect.
0
1
This bit allows the bandgap to stay powered during sleep.
0
1
Sleep interval.
00b
01b
10b
11b
These bits set the CPU clock speed, based on the system clock (SYSCLK). SYSCLK is 12 MHz by
default, but it can also be set to other frequencies (6 and 24 MHz), or driven from an external clock.
Note During USB operation, the CPU speed can be set to any setting. Be aware that USB through-
put decreases with a decrease in CPU speed. For maximum throughput, the CPU clock should be
made equal to the system clock. The system clock must be 24 MHz for USB operation.
000b
001b
010b
011b
100b
101b
110b
111b
for the proper sequence for enabling the ECO.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
The internal 32 kHz oscillator is the source of the 32K clock.
The external crystal oscillator is the source of the 32K clock.
No effect on buzz modes.
Buzz is disabled during sleep, with bandgap powered down. No periodic wakeup of the
bandgap during sleep.
Buzz bandgap during power down.
Bandgap is always powered even during sleep.
1.95 ms (512 Hz)
15.6 ms (64 Hz)
125 ms (8 Hz)
1s (1 Hz)
6 MHz IMO
750 kHz
1.5 MHz
3 MHz
6 MHz
375 kHz
187.5 kHz
46.9 kHz
23.4 kHz
No Buzz
RW : 0
5
12 MHz IMO
1.5 MHz
3 MHz
6 MHz
12 MHz
750 kHz
375 kHz
93.7 kHz
46.8 kHz
4
Sleep[1:0]
RW : 0
3
24 MHz IMO
3 MHz
12 MHz
24 MHz
1.5 MHz
750 kHz
187.5 kHz
93.7 kHz
6 MHz
2
1,E0h
CPU Speed[2:0]
RW : 010b
EXTCLK/128
External Clock
EXTCLK/8
EXTCLK/4
EXTCLK/2 (Reset State)
EXTCLK/1
EXTCLK/16
EXTCLK/32
EXTCLK/256
Register Definitions on
1
Application Overview on
0
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