CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 118

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The I
to the external I
two dedicated GPIO pins. When I
pins are not available for general purpose use. The PSoC
CPU firmware interacts with the block through I/O register
reads and writes, and firmware synchronization is imple-
mented through polling and/or interrupts.
In the default operating mode, which is firmware compatible
with previous versions of I
stalled upon every received address or byte, and the CPU is
required to read the data or supply data as required before
the I
module provides new data buffering capability as an
enhanced feature. In the EZI2C buffering mode, the I
slave interface appears as a 32-byte RAM buffer to the
external I
master controls the read and write pointers into the RAM.
When this method is enabled, the slave never stalls the bus.
In this protocol, the data available in the RAM (this is man-
aged by the CPU) is valid.
15.2
There are two modes of slave operation, which are differen-
tiated by how the I
how and when stalling of the I
ered.
15.2.1
When Slave mode is enabled, it is continually listening on
the bus for a Start condition. When detected, the transmitted
address/RW byte is received and read from the I
firmware. At the point where eight bits of the address/RW
byte are received, a byte complete interrupt is generated.
On the following low of the clock, the bus is stalled by hold-
ing the SCL line low until the PSoC device has had a chance
to read the address byte and compare it to its own address.
It Issues an ACK or NACK command based upon that com-
parison.
I2C Slave
118
2
2
C bus continues. However, this I
C block controls the data (SDA) and the clock (SCL)
2
C master. Using a simple predefined protocol, the
Application Overview
Slave Operation
START
2
C interface through direct connections to
2
C block synchronizes CPU interaction,
2
7-Bit Address
C slave modules, the I
1
2
Figure 15-2. Basic I
C bus is done, and data buff-
2
C is enabled, these GPIO
2
C Slave Enhanced
7
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
R/W
2
8
C block by
2
2
C bus is
C Data Transfer with 7-Bit Address Format
ACK
9
2
C
15.1.1
Figure 15-2
I
description, see the Philips Semiconductors (now NXP
Semiconductors) I
A Start condition (generated by the master) is followed by a
data byte, consisting of a 7-bit slave address (there is also a
10-bit address mode) and a read/write (RW) bit. The RW bit
sets the direction of data transfer. The addressed slave is
required to acknowledge (ACK) the bus by pulling the data
line low during the ninth bit time. If the ACK is received, the
transfer proceeds and the master transmits or receives an
indeterminate number of bytes, depending upon the RW
direction. If, for any reason, the slave does not respond with
an ACK, a Stop condition is generated by the master to ter-
minate the transfer or a Restart condition is generated for a
retry attempt.
If there is an address match, the RW bit determines how the
PSoC device sequences the data transfer in Slave mode, as
shown in the two branches of
methodology (slave holds the SCL line low to “stall” the bus)
is used, as necessary, to give the PSoC device time to
respond to the events and conditions on the bus.
Figure 15-3
transfer from the slave perspective.
2
1
C bus with a 7-bit address format. For a more detailed
8-Bit Data
shows the basic form of data transfers on the
is a graphical representation of a typical data
Basic I
7
2
C-Bus Specification, version 2.1.
8
2
ACK/NACK
C Data Transfer
9
Figure
STOP
15-3. I
2
C handshaking
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