CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 278

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OSC_CR2
21.4.19 OSC_CR2
This register is used to configure various features of internal clock sources and clock nets.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
page 112
Bit
4
2
1
278
Individual Register Names and Addresses:
OSC_CR2 : 1,E2h
Access : POR
Bit Name
1,E2h
CLK48MEN
EXTCLKEN
IMODIS
Name
in the Digital Clocks chapter.
Oscillator Control Register 2
7
6
Description
This is the 48 MHz clock enable bit.
0
1
External Clock Mode Enable.
0
1
Internal Oscillator Disable. This bit can be set to save power when using an external clock on P1[4].
0
1
Note This bit must not be set high in the same instruction that sets EXTCLKEN high, but it can be set
in the next instruction. Also, this bit must not be set high if the external clock frequency is less than 6
MHz.
When switching from external clock to internal clock, the IMO must be enabled for at least 10 μ s
before the transition to internal clock. Refer to
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Disables the 48 MHz clock.
Enables the 48 MHz clock.
Disabled. Operate from internal main oscillator.
Enabled. Operate from the clock supplied at P1[4] or P1[1] based upon the TSYNC bit in
CPU_SCR1.
Enabled. Internal oscillator enabled.
Disabled.
5
CLK48MEN
RW : 0
4
3
Switch Operation on page
EXTCLKEN
RW : 0
2
1,E2h
110.
IMODIS
RW : 0
Register Definitions on
1
0
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