CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 65

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3.3
The System Status and Control Register 1 (CPU_SCR1)
conveys the status and control of events related to internal
resets and watchdog reset.
Bit 7: IRESS. The Internal Reset Status bit is a read only bit
that determines if the booting process occurred more than
once.
When this bit is set, it indicates that the SROM SWBootRe-
set code ran more than once. If this bit is not set, the
SWBootReset ran only once. In either case, the SWBootRe-
set code does not allow execution from code stored in Flash
until the M8C core is in a safe operating mode with respect
to supply voltage and Flash operation. There is no need for
concern when this bit is set. It is provided for systems that
may be sensitive to boot time, so that they can determine if
the normal one pass boot time was exceeded. For more
information on the SWBootReest code, see the
ROM (SROM) chapter on page
Bit 4 to 3: SLIMO[1:0]. These bits set the IMO frequency
range. See the table below for more information.
These changes allow for optimization of speed and power.
The IMO trim value must also be changed when SLIMO is
changed (see
external clocking mode, the IMO is the source for SYSCLK;
7.3.4
The Oscillator Control Register 2 (OSC_CR2) configures
various features of internal clock sources and clock nets.
Bit 4: CLK48MEN. This is the 48 MHz clock enable bit. ‘0‘
disables the bit and ‘1‘ enables the bit. This register setting
applies only when the device is not in OCD mode. When in
OCD mode, the 48 MHz clock is always active.
Bit 2: EXTCLKEN. When the EXTCLKEN bit is set, the
external clock becomes the source for the internal clock
tree, SYSCLK, which drives most device clocking functions.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
x,FEh
LEGEND
x An “x” before the comma in the address field indicates that this register can be read or written to no matter what bank is used.
# Access is bit specific. Refer to the
1,E2h
Address
Address
CPU_SCR1
OSC_CR2
CPU_SCR1 Register
OSC_CR2 Register
Engaging Slow IMO on page
Name
Name
IRESS
Bit 7
Bit 7
Register Reference chapter on page 187
89.
Bit 6
Bit 6
63). When not in
Supervisory
Bit 5
Bit 5
CLK48MEN
Bit 4
Bit 4
for additional information.
SLIMO[1:0]
therefore, when the speed of the IMO changes so does
SYSCLK.
Bit 0: IRAMDIS. Initialize RAM Disable. This bit is a control
bit that is readable and writeable. The default value for this
bit is ‘0’, which indicates that the maximum amount of SRAM
must be initialized upon watchdog reset to a value of 00h.
When the bit is ‘1’, the minimum amount of SRAM is initial-
ized after a watchdog reset.
For additional information, refer to the
on page
All external and internal signals, including the low speed
oscillator, are synchronized to this clock source. The exter-
nal clock input is located on P1[4]. When using this input,
the pin drive mode must be set to High Z (not High Z ana-
log), such as drive mode 11b with PRT1DR bit 4 set high.
Bit 1: IMODIS. When set, the Internal Main Oscillator (IMO)
is disabled.
For additional information, refer to the
page
00
01
10
11
SLIMO
278.
Bit 3
Bit 3
257.
12
6
24
Reserved
EXTCLKEN
Bit 2
Bit 2
CY8CTMG20x, CY8CTST200
IMODIS
Bit 1
Bit 1
Internal Main Oscillator (IMO)
OSC_CR2 register on
IRAMDIS
CPU_SCR1 register
Bit 0
Bit 0
RW : 00
Access
Access
# : 0
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