Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 102
Z85C3008VSG
Manufacturer Part Number
Z85C3008VSG
Description
IC 8MHZ Z8500 CMOS SCC 44-PLCC
Manufacturer
Zilog
Series
SCCr
Specifications of Z85C3008VSG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
8MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Cpu Speed
8MHz
Digital Ic Case Style
LCC
No. Of Pins
44
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3932
Z85C3008VSG
Z85C3008VSG
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
Z85C3008VSG
Manufacturer:
Zilog
Quantity:
800
Company:
Part Number:
Z85C3008VSG
Manufacturer:
MAX
Quantity:
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UM010901-0601
4.4.3 SDLC Frame Status FIFO
This feature is not available on the NMOS version.
On the CMOS version and the ESCC, the ability to receive
high speed back-to-back SDLC frames is maximized by a
10-bit deep by 19-bit wide status FIFO. When enabled
(through WR15, bit D2), it provides a DMA the ability to
continue to transfer data into memory so that the CPU can
examine the message later. For each SDLC frame, a 14-
bit byte count and five status/error bits are stored. The byte
count and status bits are accessed through Read Regis-
ters 6 and 7. Read Registers 6 and 7 are only accessible
when the SDLC FIFO is enabled. The 10x19 status FIFO
is separate from the 8-byte Receive Data FIFO.
When the enhancement is enabled, the status in Read
Register 1 (RR1) and byte count for the SDLC frame is
stored in the 10 x 19 bit status FIFO. This allows the DMA
controller to transfer the next frame into memory while the
CPU verifies the message was properly received.
Summarizing the operation; data is received, assembled,
and loaded into the eight-byte FIFO before being trans-
ferred to memory by the DMA controller. When a flag is re-
ceived at the end of an SDLC frame, the frame byte count
from the 14-bit counter and five status bits are loaded into
the status FIFO for verification by the CPU. The CRC check-
er is automatically reset in preparation for the next frame
which can begin immediately. Since the byte count and sta-
tus are saved for each frame, the message integrity can be
verified at a later time. Status information for up to 10 frames
can be stored before a status FIFO overrun occurs.
If a frame is terminated with an ABORT, the byte count will
be loaded to the status FIFO and the counter reset for the
next frame.
FIFO Detail. For a better understanding of details of the
FIFO operation, refer to the block diagram in Figure 4-15.
SCC™/ESCC™ User’s Manual
Data Communication Modes
4-27
4
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