Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 99

• Manufacturer Part Number: Z85C3008VSG
• Description: IC 8MHZ Z8500 CMOS SCC 44-PLCC
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008VSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Cpu Speed: 8MHz
• Digital Ic Case Style: LCC
• No. Of Pins: 44
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3932; Z85C3008VSG

SCC™/ESCC™ User’s Manual
Data Communication Modes
4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)
Most bit-oriented protocols allow an arbitrary number of
bits between opening and closing flags. The SCC allows
for this by providing three bits of Residue Code in RR1.
These indicate which bits in the last three bytes transferred
from the receive data FIFO by the processor are actually
valid data bits (and not part of the frame check sequence
or CRC). Table 4-10 gives the meanings of the different
As indicated in the table, these bits allow the processor to
determine those bits in the information (and not CRC) field.
This allows transparent retransmission of the received
frame. The Residue Code bits do not go through a FIFO,
4-24
Residue Code
2
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
0
0
0
1
1
1
1
0
Change from Five to Eight
Change from Eight to Five
8B/C 7B/C 6B/C 5B/C
0
0
0
0
0
0
1
2
Previous Byte
0
0
0
0
0
0
0
Bits in
Figure 4-13. Changing Character Length
Time
0
0
0
0
0
0
Table 4-10. Residue Codes
0
0
0
0
0
13
21
29
34
39
8
8B/C 7B/C 6B/C 5B/C
codes for the four different character length options. The
valid data bits are right-justified, meaning, if the number of
valid bits given by the table is less than the character
length, then the bits that are valid are the right-most or
least significant bits. It should also be noted that the Resi-
due Code is only valid at the time when the End of Frame
bit in RR1 is set to 1.
so they change in RR1 when the last character of the
frame is loaded into the receive data FIFO. If there are any
characters already in the receive data FIFO the Residue
Code is updated before they are read by the processor.
12
20
28
33
38
3
4
5
6
7
8
8
8
7
Receive Data Buffer
Bits in Second
Previous Byte
11 10 9
19 18 17 16 15 14
27 26 25 24 23 22
32 31 30 29 28 27
37 36 35 34 33 32
6
1
2
3
4
5
6
7
5
4
0
0
1
2
3
4
3
8
0
0
0
0
1
2
7
1
6
5 Bits
8 Bits
8 Bits
5 Bits
5 Bits
8B/C 7B/C 6B/C 5B/C
8
8
8
8
8
8
8
8
Previous Byte
Bits in Third
7
7
7
7
7
7
7
UM010901-0601
5
6
6
6
6
6
2
3
4
5
5