Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 175
Z85C3008VSG
Manufacturer Part Number
Z85C3008VSG
Description
IC 8MHZ Z8500 CMOS SCC 44-PLCC
Manufacturer
Zilog
Series
SCCr
Specifications of Z85C3008VSG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
8MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Cpu Speed
8MHz
Digital Ic Case Style
LCC
No. Of Pins
44
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3932
Z85C3008VSG
Z85C3008VSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z85C3008VSG
Manufacturer:
Zilog
Quantity:
800
Company:
Part Number:
Z85C3008VSG
Manufacturer:
MAX
Quantity:
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Application Note
The Z180™ Interfaced with the SCC at MHZ
If you are running your system slower than 8 MHz, remove
the HCT74, D-Flip/Flop in front of HCT164. Connect the
inverted CSSCC to the HCT164 B input. This is a required
Flip/Flop because the Z180 timing specification on tIOD1
(Clock High to /IORQ Low, IOC=0) is maximum at 55 ns
This is longer than half the PHI clock cycle. Sample it using
the rising edge of clock, otherwise, HCT164 does not
generate the same signals.
The RESET signal feeds the SCC /RD and /WR through
HCT27 and HCT02 to supply the hardware reset signal. To
reduce the gate count, drop these gates and make the
SCC reset by its software command. The SCC software
reset - 0C0h to Write Register 9, “Hardware Reset
command” has the same effect as hardware reset by
“Hardware.”
6-40
(Continued)
/CSSCC
/RESET
/MREQ
Internal
/WAIT
Input
/WR
/RD
/M1
Ø
This circuit works when [(Lower HCT164’s CLK
4.7K
D
CK
HCT74
Figure 13. SCC I/O Read/Write Cycle Timing
Q
HCT04
HCT04
HCT04
A
B
/CLR
A
B
CLR
HCT164
CK
CK
HCT164
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Interrupt Acknowledge Cycle Timing
The primary timing differences between the Z180 and
SCC occur in the Interrupt Acknowledge cycle. The SCC
timing parameters that are significant during Interrupt
Acknowledge cycles are in Table 10. The Z180 timing
parameters are in Table 10. The reference numbers in
Tables 10 and 11 refer to Figure 13.
to Z180 /WAIT ) + tws <tCHW]
HCT04
HCT27
HCT27
HCT04
HCT02
HCT02
HCT02
HCT27
/INTACK
HCT02
To
85C30
/CE
To
85C30
/WR
To
85C30
/RD
To 85C30
/INTACK
To
Z180
/WAIT
UM010901-0601
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