Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 262

• Manufacturer Part Number: Z85C3008VSG
• Description: IC 8MHZ Z8500 CMOS SCC 44-PLCC
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008VSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Cpu Speed: 8MHz
• Digital Ic Case Style: LCC
• No. Of Pins: 44
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3932; Z85C3008VSG

UM010901-0601
DMA Request on Transmit Deactivation
Timing /DTR//REQ.
Timing implementation in the ESCC has been improved to
make it more compatible with the DMA cycle timing
(Reference Tech Manual, Section 2.5.2; DMA Request on
Transmit).
Transmission of Back-To-Back Frames with
a Shared Flag.
The ESCC provides facilities to allow transmission of
back-to-back frames with a shared flag between frames
(Figure 13).
In the ESCC, if the Automatic End Of Message (EOM)
Reset feature is enabled (WR7' D1=1), data for a second
frame is written to the transmit FIFO when Tx
Underrun/EOM interrupt has occurred. This allows
application software sufficient time to write the data to the
transmit FIFO while allowing the current frame to be
concluded with CRC and flag.
CRC err
Overrr
Availa
Receiv
End o
Frame
Char.
Error
Pari
Erro
Figure 12. Receive Interrupt Mechanism 2
Receive Char
Available In
Receive Characters or Spec
Conditi
Interr
Specia
Receive Interrupt on 1st
Special Conditions or In
Boost Your System Performance Using The Zilog ESCC
In the SCC, Transmission of Back-to-Back Frames is more
difficult because (Figure 14):
1. Data cannot be written to the transmitter at EOF until
2. Automatic EOM Reset is not available in the SCC.
a Transmit Buffer Empty interrupt is generated after
CRC has completed transmission.
Application software has to issue the “Reset
Tx/Underrun EOM” command manually. The software
overhead limits the next frame data to deliver
immediately after the preceding frame has been
concluded with CRC and Flag.
Locke
FIFO
Data
Rese
Erro
Unloc
FIFO
Data
Application Note
6-127
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