Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 94

• Manufacturer Part Number: Z85C3008VSG
• Description: IC 8MHZ Z8500 CMOS SCC 44-PLCC
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008VSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Cpu Speed: 8MHz
• Digital Ic Case Style: LCC
• No. Of Pins: 44
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3932; Z85C3008VSG

UM010901-0601
and is treated as normal data by the transmit and receive
logic.
The information field is not restricted in format or content
and can be of any reasonable length (including zero). Its
maximum length is that which is expected to arrive at the
receiver error-free most of the time. Hence, the determina-
tion of maximum length is a function of the communication
channel’s error rate. Usually the upper layer of the protocol
specifies the packet size. Although the data is always writ-
ten/read in a given character size, the Residue Code fea-
ture provides the mechanism to read any number of bits at
the end of the frame that do not make up a full character.
This allows for the data field to be an arbitrary number of
bits long.
The frame check field is used to detect errors in the received
address, control and information fields. The method used to
test if the received data matches the transmitted data, is
called a Cyclic Redundancy Check (CRC). The SCC has an
option to select between two CRC polynomials, and in SDLC
mode only the CRC-CCITT polynomial is used because the
transmitter in the SCC automatically inverts the CRC before
transmission. To compensate for this, the receiver checks
the CRC result for the bit pattern 0001110100001111. This
is consistent with bit-oriented protocols such as SDLC,
HDLC, and ADCCP and the others.
There are two unique bit patterns in SDLC mode besides
the flag sequence. They are the Abort and EOP (End of
Poll) sequence. An Abort is a sequence of seven to thir-
teen consecutive 1s and is used to signal the premature
termination of a frame. The EOP is the bit pattern
11111110, which is used in loop applications as a signal to
a secondary station that it may begin transmission.
SDLC mode is selected by setting bit D5 of WR4 to 1 and
bits D4, D3, and D2 of WR4 to 0. In addition, the flag se-
quence is written to WR7. Additional control bits for SDLC
mode are located in WR10 and WR7' (85X30).
4.4.1 SDLC Transmit
In SDLC mode, the transmitter moves characters from the
transmitter buffer (on the ESCC, four-byte transmitter
FIFO) to the Transmit Shift register, through the zero in-
serter and out to the TxD pin. The insertion of zero is com-
pletely transparent to the user. Zero insertion is done to all
transmitted characters except the flag and abort.
A SDLC frame must have the 01111110 (7E Hex) flag se-
quence transmitted before the data. This is done automat-
ically by the SCC by programming WR7 with 7EH as part
of the device initialization, enabling the transmitter, and
then writing data. If the SCC is programmed to idle Mark
(WR10 D3=1), special consideration must be taken to
transmit the opening flag. Ordinarily, it is necessary to re-
set the WR10 D3 to idle flag, wait 8-bit times, and then
write data to the transmitter. It is necessary to wait eight bit
times before writing data because ‘1s’ are transmitted
eight at a time and all eight must leave the Transmit Shift
register before a flag is loaded.
The ESCC has two improvements over the NMOS/CMOS
version to control the transmission of the flag at the begin-
ning of a frame. Additionally, the ESCC has improved fea-
tures to ease the handling of SDLC mode of operation, in-
cluding a function to deactivate the /RTS signal at the end
of the packet automatically. For these features, refer to the
next subsection, 4.4.1.2, “ESCC Enhancements for
SDLC Transmit.”
The number of bits per transmitted character is controlled
by bits D6 and D5 of WR5 and the way the data is format-
ted within the transmit buffer. The bits in WR5 allow the op-
tion of five, six, seven, or eight bits per character. In all cas-
es, the data must be right justified, with the unused bits
being ignored, except in the case of five bits per character.
When five bits per character are selected, the data may be
formatted before being written to the transmit buffer. This
allows transmission of one to five bits per character
(Table 4-2).
An additional bit, carrying parity information, is automati-
cally appended to every transmitted character by setting
bit D0 of WR4 to 1. This bit is sent in addition to the number
of bits specified in WR4 or by the data format. The parity
sense is selected by bit D1 of WR4. Parity is not normally
used in SDLC mode as the overhead of parity is unneces-
sary due to the availability of the CRC.
The SCC transmits address and control fields as normal
data and does not automatically send any address or con-
trol information. The value programmed into WR6 is used
by the receiver to compare the address of the received
frame (if address search mode is enabled), but WR6 is not
used by the transmitter. Therefore, the address is written
to the transmitter as the first byte of data in the frame.
The information field can be any number of characters
long. On the NMOS/CMOS version, the transmitter can in-
terrupt the CPU when the transmit buffer is empty. On the
ESCC, the transmitter can interrupt the CPU when the en-
try location of the Transmit FIFO is empty or when the
Transmit
NMOS/CMOS version can issue a DMA request when the
transmit buffer is empty, while the ESCC can issue a DMA
request when the entry location of the Transmit FIFO is
empty or when the Transmit FIFO is completely empty.
This allows the ESCC user to optimize the response to the
application requirements. Since the ESCC has a four byte
Transmit FIFO buffer, the Transmit Buffer Empty (TBE) bit
(D2 of RR0) will become set when the entry location of the
Transmit FIFO becomes empty. The TBE bit will reset
when a byte of data is loaded into the entry location of the
Transmit FIFO. For more details on this subject, refer to
FIFO
is
completely
SCC™/ESCC™ User’s Manual
Data Communication Modes
empty.
Also,
4-19
the
4