Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 11

• Manufacturer Part Number: Z85C3008VSG
• Description: IC 8MHZ Z8500 CMOS SCC 44-PLCC
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008VSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Cpu Speed: 8MHz
• Digital Ic Case Style: LCC
• No. Of Pins: 44
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3932; Z85C3008VSG

UM010901-0601
1.1 INTRODUCTION
The Zilog SCC Serial Communication Controller is a dual
channel, multiprotocol data communication peripheral de-
signed for use with 8- and 16-bit microprocessors. The
SCC functions as a serial-to-parallel, parallel-to-serial con-
verter/controller. The SCC can be software-configured to
satisfy a wide variety of serial communications applica-
tions. The device contains a variety of new, sophisticated
internal functions including on-chip baud rate generators,
digital phase-lock loops, and crystal oscillators, which dra-
matically reduce the need for external logic.
The SCC handles asynchronous formats, synchronous
byte-oriented protocols such as IBM
chronous bit-oriented protocols such as HDLC and IBM
SDLC. This versatile device supports virtually any serial
data transfer application (telecommunication, LAN, etc.)
The device can generate and check CRC codes in any
synchronous mode and can be programmed to check data
integrity in various modes. The SCC also has facilities for
modem control in both channels. In applications where
these controls are not needed, the modem controls can be
used for general-purpose I/O.
With access to 14 Write registers and 7 Read registers per
channel (the number of the registers varies depending on
the version), the user can configure the SCC to handle all
synchronous formats regardless of data size, number of
stop bits, or parity requirements.
Within each operating mode, the SCC also allows for pro-
tocol variations by checking odd or even parity bits, char-
acter insertion or deletion, CRC generation, checking
break and abort generation and detection, and many other
protocol-dependent features.
®
Bisync, and syn-
C
G
The SCC/ESCC family consists of the following seven
devices;
NMOS
CMOS
ESCC
EMSCC
As a convention, use the following words to distinguish the
devices throughout this document.
The Z-Bus version has a multiplexed bus interface and is
directly compatible with the Z8000, Z16C00 and 80x86
CPUs. The Universal version has a non-multiplexed bus
interface and easily interfaces with virtually any CPU, in-
cluding the 8080, Z80, 68X00.
U
ENERAL
SER
HAPTER
EMSCC: Description applies to EMSCC (Z85233)
Z85X3X: Description applies to Universal version of
Z80X30: Description applies to Z-Bus version of the
NMOS: Description applies to NMOS version
CMOS: Description applies to CMOS version
ESCC: Description applies to ESCC
SCC: Description applies to all versions.
’
S
M
ANUAL
(Z8030/Z8530)
(Z80C30/Z85C30)
(Z80230/Z85230)
device (Z8030/Z80C30/Z80230)
the device (Z8530/Z85C30/Z85230/Z85233)
D
ESCRIPTION
Z-Bus
Z8030
Z80C30
Z80230
1
®
Universal-Bus
Z8530
Z85C30
Z85230
Z85233
1-1
1