Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 247
Z85C3008VSG
Manufacturer Part Number
Z85C3008VSG
Description
IC 8MHZ Z8500 CMOS SCC 44-PLCC
Manufacturer
Zilog
Series
SCCr
Specifications of Z85C3008VSG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
8MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Cpu Speed
8MHz
Digital Ic Case Style
LCC
No. Of Pins
44
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3932
Z85C3008VSG
Z85C3008VSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z85C3008VSG
Manufacturer:
Zilog
Quantity:
800
Company:
Part Number:
Z85C3008VSG
Manufacturer:
MAX
Quantity:
74
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Application Note
Using SCC with Z8000 in SDLC Protocol
If receive overrun error is made, a special condition
interrupt occurs. The SCC presents vector %2E to the
CPU, and the service routine located at address %447A is
executed. Register RR1 is read to determine which error
occurred. Appropriate action to correct the error should be
taken by the user at this point. Error Reset and Reset
Highest IUS commands are given to the SCC before
returning to the main program so that the other low-priority
interrupts can occur.
SOFTWARE
Software routines are presented in the following pages.
These routines can be modified to include various other
options (e.g., SDLC Loop, Digital Phase Locked Loop
6-112
RECEIVE OPERATION (Continued)
In addition to searching the data stream for flags, the
receiver also scans for seven consecutive 1s, which
indicates an abort condition. This condition is reported in
the Break/Abort bit (D7) in RR0. This is one of many
possible external status conditions. As a result transitions
of this bit can be programmed to cause an external status
interrupt. The abort condition is terminated when a zero is
received, either by itself or as the leading zero of a flag.
The receiver leaves Hunt mode only when a flag is found.
etc.). By modifying the WR10 register, different encoding
methods (e.g., NRZI, FM0, FM1) other than NRZ can be
used.
UM010901-0601
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