PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 115

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
S-Bus D-channel Access Control in the SBCX-X
The above described priority mechanism is fully implemented in the SBCX-X. For this
purpose the D-channel collision detection according to ITU I.430 must be enabled by
setting TR_MODE2.DIM2-0 to ’0x1’. In this case the transceiver continuously compares
the received E-echo bits with its own transmitted D data bits.
Depending on the priority class selected, 8 (priority 8) or 10 (priority 10) consecutive
ONEs (high priority level) need to be detected before the transceiver sends valid D-
channel data on the upstream D-bits on S. In low priority level 9 (priority 8) or 11 (priority
10) consecutive ONEs are required.
The priority class (priority 8 or priority 10) is selected by transferring the appropriate
activation command via the Command/Indication (C/I) channel of the IOM-2 interface to
the transceiver. If the activation is initiated by a TE, the priority class is selected implicitly
by the choice of the activation command. If the S-interface is activated from the NT, an
activation command selecting the desired priority class should be programmed at the TE
on reception of the activation indication (AI8 or AI10). In the activated state the priority
class may be changed whenever required by simply programming the desired activation
request command (AR8 or AR10).
3.7.5.3
If the TE frame structure on the IOM-2 interface is selected, the same D-channel access
procedures as described in
For other frame structures used in LT-T mode, D-channel access on S is handled
similarly, with the difference that the S/G bit is not available on IOM-2 but only on the
S/G bit output pin (SGO).
3.7.5.4
In intelligent NT applications (selected via register TR_MODE.MODE2-0) one or more
D-channel controllers on the IOM-2 interface share the upstream D-channel with all
connected TEs on the S interface.
The transceiver incorporates an elaborate statemachine for D-channel priority handling
on IOM-2. For the access to the D-channel a similar arbitration mechanism as on the S
interface (writing D-bits, reading back E-bits) is performed for all D-channel sources on
IOM-2. Due to this an equal and fair access is guaranteed for all D-channel sources on
both the S interface and the IOM-2 interface.
This arbitration mechanism is only available in IOM-2 TE mode (12 PCM timeslots) per
frame with enabled TIC bus. The access to the upstream D-channel is handled via the
S/G bit for the HDLC controllers and via E-bit for all connected terminals on S (E-bits are
inverted to block the terminals on S). Furthermore, if more than one HDLC source is
requesting D-channel access on IOM-2 the TIC bus mechanism is used.
Data Sheet
S-Bus D-Channel Control in LT-T
D-Channel Control in the Intelligent NT (TIC- and S-Bus)
Chapter 3.7.5.2
115
are used in LT-T mode.
Description of Functional Blocks
PEB 3081
PEF 3081
2000-09-27