PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 116

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
The arbiter permanently counts the “1s” in the upstream D-channel on IOM-2. If the
necessary number of “1s” is counted and an HDLC controller on IOM-2 requests
upstream D-channel access (BAC bit is set to 0), the arbiter allows this D-channel
controller immediate access and blocks other TEs on S (E-bits are inverted). Similar as
on the S-interface the priority for D-channel access on IOM-2 can be configured to 8 or
10 (TR_CMD.DPRIO).
The upstream device can stop all D-channel sources by setting the A/B-bit to 0. The S/
G bit is not evaluated in this mode.
The configuration settings of the SBCX-X in intelligent NT applications are summarized
in
Table 12
Note: For mode selection in the TR_MODE register the MODE1/2 bits are used to select
With the configuration settings shown above the SBCX-X in intelligent NT applications
provides for equal access to the D-channel for terminals connected to the S-interface
and for D-channel sources on IOM-2.
For a detailed understanding the following sections provide a complete description on
the procedures used by the D-channel priority handler on IOM-2, although it may not be
necessary to study that in order to use this mode.
Data Sheet
Configuration Description
Select intelligent NT mode
Enable S/G bit evaluation
Table
intelligent NT mode, MODE0 selects NT or LT-S state machine.
12.
SBCX-X Configuration Settings in Intelligent NT Applications
Configuration Setting
Transceiver Mode Register 2:
Transceiver Mode Register:
TR_MODE.MODE0 = 0 (NT state machine)
or
TR_MODE.MODE0 = 1 (LT-S state machine)
TR_MODE.MODE1 = 1
TR_MODE.MODE2 = 1
TR_MODE2.DIM2-0 = 001
116
Description of Functional Blocks
PEB 3081
PEF 3081
2000-09-27