PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 90

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

PEB 3081
PEF 3081
Description of Functional Blocks
Preliminary
Figure 45
shows the timing of looping TSa from DU to DD (a = 0...31) via CDAxy
register. TSa is read in the CDAxy register from DU and is written one frame later on DD.
.
a = 0...31
FSC
DU
TSa
TSa
CDAxy
*)
µC
DD
TSa
TSa
*) if access by the µC is required
Figure 45
Data Access when Looping TSa from DU to DD
Figure 46
shows the timing of shifting data from TSa to TSb on DU (DD). In
Figure 46a)
shifting is done in one frame because TSa and TSb didn’t succeed direct one another (a,
b = 0...29 and b  a+2 In
Figure 46b)
shifting is done from one frame to the following
frame. This is the case when the time slots succeed one other (b = a+1) or b is smaller
than a (b < a).
At looping and shifting the data can be accessed by the controller between the
synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). STI and
STOV are explained in the section ’Synchronous Transfer’. If there is no controller
intervention the looping and shifting is done autonomous.
Data Sheet
90
2000-09-27