PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 139

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

PEB 3081
PEF 3081
Detailed Register Description
Preliminary
4.1.9
TR_STA - Transceiver Status Register
Value after reset: 00
H
7
0
TR_
RINF
SLIP
ICV
0
FSYN
0
LD
RD (33)
STA
Important: This register is used only if the Layer 1 state machine of the SBCX-X is
disabled (TR_CONF0.L1SW = 1) and implemented in software! With the SBCX-X layer
1 state machine enabled, the signals from this register are automatically evaluated.
For general information please refer to
Chapter
3.5.
RINF ... Receiver INFO
00: Received INFO 0
01: Received any signal except INFO 1 - 4
10: Received INFO 1 (NT mode) or INFO 2 (TE mode)
11: Received INFO 3 (NT mode) or INFO 4 (TE mode)
SLIP ... SLIP Detected
A ’1’ in this bit position indicates that a SLIP is detected in the receive or transmit path.
ICV ... Illegal Code Violation
0: No illegal code violation is detected
1: Illegal code violation (ANSI T1.605) in data stream is detected
FSYN ... Frame Synchronization State
0: The S/T receiver is not synchronized
1: The S/T receiver has synchronized to the framing bit F
LD ... Level Detection
0: No receive signal has been detected on the line.
1: Any receive signal has been detected on the line.
Data Sheet
139
2000-09-27