PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 166

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
4.4
4.4.1
Value after reset: 00
ISTA
For all interrupts in the ISTA register following logical states are applied:
0: Interrupt is not acitvated
1: Interrupt is acitvated
ST ... Synchronous Transfer
This interrupt is generated to enable the microcontroller to lock on to the IOM timing for
synchronous transfers. The source can be read from the STI register.
CIC ... C/I Channel Change
A change in C/I channel 0 or C/I channel 1 has been recognized. The actual value can
be read from CIR0 or CIR1.
AUX ... Auxiliary Interrupts
Signals an interrupt generated from external awake (pin EAW), watchdog timer overflow
(WOV) or from the timer (TIN). The source can be read from the auxiliary interrupt
register AUXI.
TRAN ... Transceiver Interrupt
An interrupt originated in the transceiver interrupt status register (ISTATR) has been
recognized.
MOS ... MONITOR Status
A change in the MONITOR Status Register (MOSR) has occured.
Note: A read of the ISTA register clears none of the interrupts. They are only cleared by
Data Sheet
reading the corresponding status register.
7
Interrupt and General Configuration
ISTA - Interrupt Status Register
0
H
0
ST
CIC
166
AUX
TRAN MOS
Detailed Register Description
0
0
PEB 3081
PEF 3081
2000-09-27
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