PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 153

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
4.3.4
Value after reset: F8
TR_CR
Read and write access to this register is only possible if IOM_CR.CI_CS = 0.
EN_D ... Enable Transceiver D-Channel Data
EN_B2R ... Enable Transceiver B2 Receive Data
EN_B1R ... Enable Transceiver B1 Receive Data
EN_B2X ... Enable Transceiver B2 Transmit Data
EN_B1X ... Enable Transceiver B1 Transmit Data
This register is used to individually enable/disable the D-channel (both RX and TX
direction) and the receive/transmit paths for the B-channels of the S-transceiver.
0: The corresponding data path to the transceiver is disabled.
1: The corresponding data path to the transceiver is enabled.
Note: “Receive Data” refers to the data which is received on the S interface and
CS2-0 ... Channel Select for Transceiver D-channel
This register is used to select one of eight IOM channels to which the transceiver D-
channel data is related to.
Note: The reset value is determined by the channel select pins CH2-0 which are directly
Data Sheet
forwarded to IOM-2. “Transmit data” refers to the data which is coming from
IOM-2 and transmitted on the S interface.
mapped to CS2-0. It should be noted that writing TR_CR.CS2-0 will also write to
TRC_CR.CS2-0 and therefore modify the channel selection for the transceiver
C/I0 data.
7
TR_CR - Control Register Transceiver Data (IOM_CR.CI_CS=0)
EN_
D
EN_
B2R
H
EN_
B1R
EN_
B2X
153
EN_
B1X
Detailed Register Description
CS2-0
0
RD/WR (50)
PEB 3081
PEF 3081
2000-09-27