PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 100

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
2.6.3
Data transfer between the system memory and the IPAC for both transmit and receive
direction is controlled either by interrupts (Interrupt Mode), or independently from host
interaction using the IPAC’s 4-channel DMA interface (DMA Mode). DMA transfer is
available for transfer of B-channel data only and not for D-channel data.
After RESET, the IPAC operates in Interrupt Mode, where data transfer must be done by
the host. The user selects the DMA Mode by setting the DMA bit in a register. In TE mode
both channels can independently be operated in either Interrupt or DMA Mode (e.g.
Channel A in DMA mode, Channel B in interrupt mode). In LT-S and LT-T mode, only
channel B can be operated either in Interrupt or DMA mode, channel A can only be
operated in Interrupt mode.
2.6.4
Special events in the IPAC are indicated by means of a single interrupt output, which
requests the host to read status information from the IPAC or transfer data from/to the
IPAC.
Two interrupt lines with invers polarity are available to meet the requirements of different
kinds of applications. A low active interrupt output INT (pin 2) can be connected to a pull
up resistor together with further interrupt sources on the system. This pin is available in
all modes.
The inverted interrupt signal is available in TE mode only if pin AUX2 (pin 33) is
programmed as output (see chapter 2.8.1). This may be used in single chip solutions
(e.g. PC cards) with only one interrupt source that can directly be connected to the ISA
bus. This high active interrupt line INT is not available in LT-modes and in TE-mode with
AUX2 used as input (default after reset).
Figure 38
Since only one interrupt request output is provided, the cause of an interrupt must be
determined by the host reading the IPAC’s interrupt status registers.
The structure of the interrupt status registers is shown in figure 39.
Data Transfer Mode
Interrupt Interface
TE-Mode
High and Low Active Interrupt Output
Interrupt
IPAC
33
2
INT
INT
100
LT-Modes
Interrupt
IPAC
2
Functional Description
INT
2115_3
PSB 2115
PSF 2115
11.97