PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 91

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

frame is shifted by two bits with respect to the received frame.
In TE mode the output clocks (DCL, FSC etc.) are synchronous to the S interface timing.
In LT-T mode the IPAC provides a 1.536 MHz clock on the SCLK pin synchronous to the
S interface. This can be used as the reference clock for an external PLL which provides
the FSC and DCL clocks. Since the IPAC provides different dividers, the clocks can also
be generated internally from the DCL input connected to SCLK (see chapter 2.8.2.2).
TE and LT-T
In TE/LT-T applications, the transmit and receive bit clocks are derived, with the help of
the DPLL, from the S interface receive data stream. The received signal is sampled
several times inside the derived receive clock period, and a majority logic is used to
additionally reduce bit error rate in severe conditions (see chapter 2.5.3). The transmit
Figure 33
Semiconductor Group
Clock System of the IPAC in TE and LT-T Modes
LT-T Mode
SCLK
TE Mode
PLL
BCL
PLL
Detector
Slip
91
FSC
DCL
DCL
FSC
(PLL)
"NT2" Clock
Generator
Functional Description
Reference
Clock
ITS09634
PSB 2115
PSF 2115
11.97