PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 223

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
The cyclic transmission continues until the command XRES is executed or the bit XREP
is reset. The interframe timefill pattern is issued afterwards. When resetting XREP, data
transmission is stopped after the next XFIFOB-cycle is completed, the XRES command
terminates data transmission immediately .
Note: MODEB:CFT must be set to ’0’ when using cyclic transmission.
XTF … Transmit Transparent Frame
After having written up to 64 bytes to the XFIFOB, this command initiates the
transmission of a transparent frame. An opening flag sequence is automatically added
to the data by the IPAC (only in non-automode, transparent mode 0,1).
No opening flag sequence is generated in extended transparent mode 0, 1.
XME … Transmit Message End (used in interrupt mode only!)
Indicates, that the data block written last to the transmit FIFO completes the actual
frame. The IPAC can terminate the transmission operation properly by appending the
CRC and the closing flag sequence to the data.
Note: In DMA mode the XME must not be used.
XRES … Transmit Reset
The content of the XFIFOB is deleted and IDLE is transmitted. This command can be
used by the CPU to abort a frame currently in transmission. After setting XRES an XPR
interrupt is generated in every case.
4.2.7
Value after reset: 00
MODEB
MDS1, MDS0 … Mode Select
The operating mode of the HDLC controller is selected.
01 … non-auto mode
10 … transparent mode
11 … extended transparent mode
MDS1 MDS0 ADM
MODEB - Mode Register for B-Channel (READ/WRITE)
7
H
CFT
223
RAC
0
Detailed Register Description
0
0
TLP
PSB 2115
PSF 2115
(22/62)
11.97