PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 199

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
S/T-Interface Signals
I0
I1
I3
It
States TE/LT-T Mode
F3 power down
This is the deactivated state of the physical protocol. The received line awake unit is
active. In TE mode, clocks are disabled if the CFS bit of the IPAC Configuration Register
is set to “1“.
F3 power up
This state is similar to “F3 power down”. The state is invoked by a C/I command
TIM = “0000” (or DU static low). After the subsequent activation of the clocks the “Power
Up” message is output.
F3 pending deactivation
The IPAC reaches this state after receiving INFO0 (from states F5 to F8) from F6 and
F7 via F5/8. From this state an activation is only possible from the line (transition “F3
pend. deact.” to “F5 unsynchronized”). The power down state may be reached only after
receiving DI.
F4 pending activation
Activation has been requested from the terminal, INFO 1 is transmitted, INFO 0 is still
received, “Power Up” is transmitted in the C/I channel. This state is stable: timer T3
(I.430) is to be implemented in software.
F5/8 unsynchronized
At the reception of any signal from the NT, the IPAC ceases to transmit INFO 1, adapts
its receiver circuit, and awaits identification of INFO 2 or INFO 4. This state is also
reached after the IPAC has lost synchronism in the states F6 or F7 respectively.
INFO 0
INFO 1
INFO 3
Pseudo-ternary pulses at 2 kHz frequency (alternating, TM1)
Pseudo-ternary pulses at 96 kHz frequency (alternating, TM2)
199
Operational Description
PSB 2115
PSF 2115
11.97