PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 222

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

CMDRB
the contents of the XFIFOB (1 … 64 bytes) without HDLC framing fully transparent, i.e.
without FLAG, CRC insertion, bit stuffing.
AFI … Additional Frame Indication
A ’1’ indicates, that one or more completely received frames or the last part of a frame
are in the CPU inaccessible part of the RFIFOB. In combination with the bit STARB:RFR
multiple frames can be read out of the RFIFOB without interrupt control.
4.2.6
Value after reset: 00
Note: The maximum time between writing to the CMDRB register and the execution of
RMC … Receive Message Complete
Confirmation from CPU to IPAC, that the actual frame or data block has been fetched
following an RPF or RME interrupt, thus the occupied space in the RFIFOB can be
released.
Note: In DMA mode this command is only issued once after an RME interrupt. The IPAC
RHR … Reset HDLC Receiver
All data in the RFIFOB and the HDLC receiver is deleted.
XREP … Transmission Repeat
In extended transparent mode 0, 1 :
Together with XTF and XME set (write 2 A
Semiconductor Group
the command is 2.5 clock cycles. Therefore, if the CPU operates with a very high
clock in comparison with the IPAC’s clock, it’s recommended that the CEC bit of
the STARB register is checked before writing to the CMDRB register to avoid any
loss of commands.
does not generate further DMA requests prior to the reception of this command.
CMDRB - Command Register for B-Channel (WRITE)
7
RMC
RHR XREP
H
0
222
H
XTF
to CMDRB), the IPAC repeatedly transmits
0
Detailed Register Description
XME XRES
0
PSB 2115
PSF 2115
(21/61)
11.97