PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 161

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PSB2115HV1.2

Manufacturer Part Number
PSB2115HV1.2
Description
Manufacturer
Lantiq
Datasheet

Specifications of PSB2115HV1.2

Lead Free Status / Rohs Status
Supplier Unconfirmed

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Semiconductor Group
General IPAC registers
Register
CONF
PCFG
PITA1/2
Bit
ODS
IOF
IDH
CFS
AMP
TEM
PDS
SGO
PLD
CSL2-0
FBS
ACL
LED
ENA
DUDD
TNRX
Effect
DU/DD output driver selection (open
drain or push pull)
IOM interface off or operational
Enable/disable IOM-2 D-Channel
priority handler
Clock relations and recovery on S/T
interface
Transformer ratio
Tests mode (disable layer-1 function)
Select phase deviation of the S-
interface.
S/G bit output on pin AUX7
PCM interface enable/disable
IOM Channel Select for PCM
interface
FSC or BCL output on pin AUX3
Pin ACL as indication for S-bus
activation or as programmable output
Output value on ACL (if enabled)
Enable PCMIN channel
Map data on DU/DD
Timeslot number select
161
Operational Description
Application
LT-S mode
(intelligent NT)
TE and LT-T mode
LT-S and LT-T mode
LT modes
LT modes
LT modes
all modes
all modes
PCM interface
(LT modes)
PSB 2115
PSF 2115
11.97

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