PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 197

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
Pin States
Pin-RES Pin-Reset. Corresponds to a high level at pin RST. At power up, a reset pulse
S/T-Interface Events
I0
I0
I2
I4
SLIP
Transmitted Signals and Indications in TE/LT-T Modes
The following signals and indications are issued on the IOM-2 and S/T-interface.
INFO 0 detected
A signal different to INFO 0 was detected
INFO 2 detected
INFO 4 detected
SLIP detected (applicable in LT-T mode only) IOM-2 interface framing and
S/T-interface framing differences have exceeded the specified limit. It is likely
that data will be lost to enable a resynchronization.
(RST high active) of minimum 2 DCL clock cycles should be applied to bring
the IPAC to the state “reset”. After that the IPAC may be operated according
to the state diagrams. In NT mode the DCL is needed during the hardware
reset (RES = 1) for initialization. The function of this pin is identical to the C/I
code RES concerning the state machine.
197
Operational Description
PSB 2115
PSF 2115
11.97