PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 278

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

TLEN ... Timeslot Length
0: 8 bit
1: 16 bit
TSLT ... Timeslot Position
Selects one of 32 timeslots on the IOM-2 interface (with respect to FSC) during which
SDS is active high. The data strobe signal allows standard data devices to access a
programmable channel.
4.4.13
Value after reset: 00
TIMR2
TMD ... Timer Mode
Timer 2 can be used in two different modes of operation.
0: Count down timer. An interrupt is generated only once after a time period of 1 ... 63 ms.
1: Periodic timer. An interrupt is periodically generated every 1 ... 63 ms (see CNT).
CNT ... Timer Count
0:
1 ... 63:
By writing ’0’ to CNT, the timer is immediately stopped. A value different from that
determines the time period after which an interrupt will be generated.
If the timer is already started with a certain CNT value and is written again before an
interrupt has been released, the timer will be reset to the new value and restarted again.
An interrupt is indicated to the host in ISTAD:TIN2.
Semiconductor Group
Timer off
Timer length = 1 ... 63 ms
TIMR2 - Timer 2 Register (Read/Write)
7
TMD
H
0
278
CNT
Detailed Register Description
0
PSB 2115
PSF 2115
11.97
(CC)