PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 11

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PSB 2115
PSF 2115
List of Figures
Page
Figure 78: IPAC Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 79: a) CIC Interrupt Structure
b) MOS Interrupt Structure
172
Figure 80: Interrupt Driven Data Transmission (Flow Diagram) . . . . . . . . . . . . . . . 175
Figure 81: Interrupt Driven Transmission Sequence Example . . . . . . . . . . . . . . . . 176
Figure 82: Continuous Frames Transmission (Flow Diagram) . . . . . . . . . . . . . . . . 177
Figure 83: Continuous Frames Transmission Sequence Example . . . . . . . . . . . . . 178
Figure 84: DMA Driven Transmission Sequence Example . . . . . . . . . . . . . . . . . . . 179
Figure 85: Interrupt Driven Reception Sequence Example . . . . . . . . . . . . . . . . . . . 181
Figure 86: DMA Driven Reception Sequence Example. . . . . . . . . . . . . . . . . . . . . . 182
Figure 87: Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 88: Transmission of an I Frame in the D Channel (Subscriber to Exchange) 185
Figure 89: Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 90: Deactivation of the IOM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 91: Activation of the IOM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 92: State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 93: State Transition Diagram in TE/LT-T Modes . . . . . . . . . . . . . . . . . . . . . 194
Figure 94: State Diagram of the TE/LT-T Modes, Unconditional Transitions . . . . . 195
Figure 95: State Transition Diagram in LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 96: NT Mode State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 97: Example of Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 98: Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 99: Test Condition for Maximum Input Current. . . . . . . . . . . . . . . . . . . . . . . 279
Figure 100:Maximum Line Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Figure 101:Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 102:Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Figure 103:Microprocessor Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Figure 104:Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Figure 105:Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Figure 106:Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 107:Microprocessor Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 108:Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 109:Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 110:IOM Timing (TE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Figure 111:IOM Timing (LT-S, LT-T mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Figure 112:PCM Interface Timing (LT-S, LT-T mode) . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 113:BCL, FSC Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Figure 114:AUX Interface I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 115:Phase Relationships of IPAC Clock Signals. . . . . . . . . . . . . . . . . . . . . . 294
Figure 116:Definition of Clock Period and Width . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Figure 117:Block Diagram of XPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Figure 118:Reset Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Semiconductor Group
11
11.97