PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 276

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

TNTX ... Time Slot Number Transmit
Selects one of up to 32 possible timeslots (00h-1Fh) in which data is transmitted to the
PCM interface.
Note: The configuration of the PCM timeslots is equal for B1 and B2-channel.
4.4.11
Value after reset: 00
PCFG
DPS ... Data Path Select
Data from the B-channel FIFOs is exchanged with the
0: IOM-2 interface
1: PCM interface
ACL ... ACL Function Select
0: pin ACL indicates the S-bus activation status by a LOW level
1: the state at pin ACL is programmable by the host via bit LED.
LED ... LED Control
If enabled (ACL=1) the LED connected to pin ACL is switched
0: Off
1: On
Note: The state (log. high/low) on pin ACL is derived from the inverted state of
PLD ... PCM Lines Disable (LT-S and LT-T modes)
0: AUX3-5 are used for PCM interface (default)
1: AUX3-5 are used as normal I/O lines (PCM interface disabled)
Note: In TE mode PLD must be set to ’1’ before AUX3-5 are used as I/O lines.
Semiconductor Group
PCFG:LED. For ACL=0 the state of PCFG:LED has no effect.
PCFG - PCM Configuration Register (Read/Write)
7
DPS
ACL
H
LED
PLD
276
FBS
CSL2 CSL1 CSL0
Detailed Register Description
0
PSB 2115
PSF 2115
11.97
(CA)