PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 141

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PSB 2115
PSF 2115
Functional Description
2.7.6
TIC Bus Access
In IOM-2 interface mode the TIC bus capability is only available in TE mode. The
arbitration mechanism implemented in the last octet of IOM channel 2 of the IOM-2
interface allows the access of external communication controllers (up to 7) to the layer-
1 functions provided in the IPAC and to the D channel. (TIC bus; see figure 66). To this
effect the outputs of the controllers (ICC:ISDN Communication Controller PEB 2070) are
wired-or-and connected to pin DU. The inputs of the ICCs are connected to pin DD.
External pull-up resistors on DU/DD are required. The arbitration mechanism must be
activated by setting MODED:DIM2-0=001.
An access request to the TIC bus may either be generated by software ( P access to
the C/I channel) or by the IPAC itself (transmission of an HDLC frame in the D-channel).
A software access request to the bus is performed by setting CIX0:BAC=1 bit which has
the effect that the BAC bit on the DU line (bit 5 of last octet of Ch2, see figure 67) is tied
to "0" (i.e. "TIC bus is occupied").
In the case of an access request, the IPAC checks the Bus Accessed-bit BAC on DU for
the status "bus free", which is indicated by a logical "1". If the bus is free, the IPAC
transmits its individual TIC bus address programmed in the STCR register. The IPAC
sends its TIC bus address TAD and compares it bit by bit with the value on DU. If a sent
bit set to ’1’ is read back as ’0’ because of the access of another D-channel source with
a lower TAD, the IPAC withdraws immediately from the TIC bus. The TIC bus is occupied
by the device which sends its address error-free. If more than one device attempt to
seize the bus simultaneously, the one with the lowest address values wins. This one will
set BAC=0 on TIC bus and starts D-channel transmission.
Figure 67
Structure of Last Octet of Ch2 on DU
When the TIC bus is seized by the IPAC, the bus is identified to other devices as
occupied via the DU Ch2 Bus Accessed-bit state "0" until the access request is
Semiconductor Group
141
11.97