PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 268

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.4
4.4.1
Value after reset: 00
CONF
AMP ... Amplification of S/T receiver
0: an external transformer of ratio 2:1 is connected to the receive lines.
1: an external transformer of ratio 1:1 is connected to the receive lines.
CFS ... Configuration Select
This bit determines clock relations and recovery on S/T and IOM interfaces.
• TE and LT-T Modes
• LT-S Mode
Semiconductor Group
0: The IOM interface clock and frame signals are always active, "Power Down" state
included.
The states "Power Down" and "Power Up" are thus functionally identical except for
the indication: PD = 1111 and PU = 0111.
With the C/I command Timing (TIM) the processor can enforce the "Power Up"
state.
With C/I command Deactivation Indication (DIU) the "Power Down" state is reached
again.
However, it is also possible to activate the S-Interface directly with the C/I command
Activate Request (AR 8/10/L) without the TIM command.
1: The IOM interface clock and frame signals are normally inactive ("Power Down").
For activating the IOM-2 clocks the "Power Up" state can be induced by software
(SPU-bit in SPCR register) or by resetting again CFS.
After that the S-interface can be activated with the C/I command Activate Request
(AR 8/10/L). The "Power Down" state can be reached again with the C/I command
Deactivation Indication (DIU).
Note: After reset the IOM interface is always active. To reach the "Power Down"
CFS has to be set to "0" always.
state the CFS-bit has to be set.
General IPAC Registers
CONF - IPAC Configuration Register (Read/Write)
7
AMP
CFS
H
TEM
PDS
268
IDH
SGO
Detailed Register Description
ODS
0
IOF
PSB 2115
PSF 2115
11.97
(C0)