PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet
PI7C8150AMAE
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PI7C8150AMAE Summary of contents
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PI7C8150A 2-PORT PCI-to-PCI BRIDGE st 3545 North 1 Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, (1-877-737-4266) Fax: 408-435-1100 Internet: http://www.pericom.com REVISION 1.1 ...
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... A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product ...
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REVISION HISTORY Date Revision Number 10/15/03 1.00 05/20/05 1.01 04/20/06 1.1 06-0057 Description First Release of Data Sheet Corrected VDD and VSS pin assignments in Section 2.2.7. Removed pins 106 and 155 (R16 and B14) as these should be MS1 ...
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This page intentionally left blank. 06-0057 2-PORT PCI-TO-PCI BRIDGE Page 4 of 111 APRIL 2006 – Revision 1.1 PI7C8150A ...
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TABLE OF CONTENTS 1 INTRODUCTION................................................................................................. 11 2 SIGNAL DEFINITIONS...................................................................................... 12 2 ............................................................................................................................... 12 IGNAL YPES 2.2 S ........................................................................................................................................ 12 IGNALS 2.2.1 PRIMARY BUS INTERFACE SIGNALS .......................................................................... 12 2.2.3 CLOCK SIGNALS ............................................................................................................... 15 2.2.4 MISCELLANEOUS SIGNALS........................................................................................... 16 2.2.5 GENERAL ...
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TARGET DISCONNECT ................................................................................................ 40 3.8.4.3 TARGET ABORT ............................................................................................................ 40 4 ADDRESS DECODING....................................................................................... 41 4.1 ADDRESS RANGES ................................................................................................................... 41 4.2 I/O ADDRESS DECODING........................................................................................................ 41 4.2.1 I/O BASE AND LIMIT ADDRESS REGISTER................................................................ 42 4.2.2 ISA MODE........................................................................................................................... 43 4.3 MEMORY ADDRESS DECODING ...
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GPIO CONTROL REGISTERS............................................................................................... 70 10.2 SECONDARY CLOCK CONTROL........................................................................................ 70 10.3 LIVE INSERTION ................................................................................................................... 72 11 PCI POWER MANAGEMENT .......................................................................... 72 12 RESET ................................................................................................................... 73 12.1 PRIMARY INTERFACE RESET ............................................................................................ 73 12.2 SECONDARY INTERFACE RESET...................................................................................... 74 12.3 CHIP RESET............................................................................................................................ 74 ...
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SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET 4Ch .......................................................................................................................................... 89 14.1.34 UPSTREAM ( MEMORY BASE REGISTER – OFFSET 50h ........................ 89 14.1.35 UPSTREAM ( MEMORY LIMIT REGISTER – OFFSET 50h....................... 90 14.1.36 UPSTREAM (S ...
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PACKAGE INFORMATION............................................................................ 109 18.1 208-PIN FQFP PACKAGE DIAGRAM ................................................................................ 109 18.2 256-BALL PBGA PACKAGE DIAGRAM ........................................................................... 110 18.3 PART NUMBER ORDERING INFORMATION.................................................................. 110 LIST OF TABLES T 2- – 208- FQFP .......................................................................................................... 18 ABLE IN IST PIN ...
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INTRODUCTION Product Description The PI7C8150A is an enhanced PCI-to-PCI Bridge is designed to be fully compliant with the PCI Local Bus Specification Revision 2.3. Both the primary and secondary interfaces are specified to run at 32-bits and up to ...
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SIGNAL DEFINITIONS 2.1 Signal Types Signal Type STS OD 2.2 Signals Note: Signal names that end with “_L” are active LOW. 2.2.1 PRIMARY BUS INTERFACE SIGNALS Name P_AD[31:0] P_CBE[3:0] P_PAR 06-0057 Description Input Only Output ...
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Name P_FRAME_L P_IRDY_L P_TRDY_L P_DEVSEL_L P_STOP_L P_LOCK_L P_IDSEL P_PERR_L P_SERR_L P_REQ_L P_GNT_L P_RESET_L 06-0057 Pin # Pin # Type 80 P9 STS 82 T10 STS 83 R10 STS 84 P10 STS 85 T11 STS 87 R11 STS ...
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Name P_M66EN 2.2.2 SECONDARY BUS INTERFACE SIGNALS Name S_AD[31:0] S_CBE[3:0] S_PAR S_FRAME_L S_IRDY_L S_TRDY_L 06-0057 Pin # Pin # Type 102 R14 I Pin # Pin # Type 206, 204, 203, A4, D5, C5, TS 201, 200, 198, A5, B5, ...
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Name S_DEVSEL_L S_STOP_L S_LOCK_L S_PERR_L S_SERR_L S_REQ_L[8:0] S_GNT_L[8:0] S_RESET_L S_M66EN S_CFN_L 2.2.3 CLOCK SIGNALS Name P_CLK S_CLKIN 06-0057 Pin # Pin # Type 175 A11 STS 173 B11 STS 172 C11 STS 171 A12 STS 169 D11 ...
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Name S_CLKOUT[9:0] 2.2.4 MISCELLANEOUS SIGNALS Name MSK_IN P_VIO S_VIO BPCCE CFG66 / SCAN_EN_H 06-0057 Pin # Pin # Type 42, 41, 39, 38, 36, M3, M2, N1, O 35, 33, 32, 30, 29 L4, L3, M1, L2, L1, K3, K2 ...
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MS0, MS1 2.2.5 GENERAL PURPOSE I/O INTERFACE SIGNALS Name GPIO[3:0] 2.2.6 JTAG BOUNDARY SCAN SIGNALS Name TCK TMS TDO TDI TRST_L 2.2.7 POWER AND GROUND Name VDD VSS 06-0057 155, 106 B14, R16 I Pin # Pin # Type 24, ...
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Name 2.3 PIN LIST – 208-PIN FQFP Table 2-1. Pin List – 208-pin FQFP Pin Number Name 1 VDD 3 S_REQ_L[2] 5 S_REQ_L[4] 7 S_REQ_L[6] 9 S_REQ_L[8] 11 S_GNT_L[1] 13 S_GNT_L[2] 15 S_GNT_L[4] 17 S_GNT_L[6] 19 S_GNT_L[8] 21 S_CLKIN 23 ...
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Pin Number Name 67 P_AD[23] 69 VDD 71 P_AD[20] 73 P_AD[19] 75 VDD 77 P_AD[16] 79 P_CBE[2] 81 VDD 83 P_TRDY_L 85 P_STOP_L 87 P_LOCK_L 89 P_SERR_L 91 VDD 93 P_AD[15] 95 P_AD[14] 97 VDD 99 P_AD[11] 101 P_AD[10] 103 ...
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Pin Number Name 191 S_AD[22] 193 VSS 195 S_AD[24] 197 S_AD[25] 199 VSS 201 S_AD[28] 203 S_AD[29] 205 VSS 207 S_REQ_L[0] 2.4 PIN LIST – 256-BALL PBGA Table 2-2. Pin List – 256-pin PBGA Pin Name Number A1 VSS A4 ...
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Pin Name Number J2 GPIO[2] J5 VDD J8 VSS J11 VSS J14 RESERVED K1 GPIO[0] K4 VDD K7 VSS K10 VSS K13 VDD K16 CFG66 SCAN_EN_H L3 S_CLKOUT[5] L6 VSS L9 VSS L10 VSS L13 P_AD[4] L16 P_AD[0] M3 S_CLKOUT[9] ...
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TYPES OF TRANSACTIONS This section provides a summary of PCI transactions performed by PI7C8150A. Table 3-1 lists the command code and name of each PCI transaction. The Master and Target columns indicate support for each transaction when PI7C8150A initiates ...
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If either of the lowest two address bits is non-zero, PI7C8150A automatically disconnects the transaction after the first data transfer. 3.3 DEVICE SELECT (DEVSEL_L) GENERATION PI7C8150A always performs positive address decoding (medium decode) when accepting transactions on either the primary ...
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The PI7C8150A can accept one DWORD of write data every PCI clock cycle. That is, no target wait state is inserted. The write data is stored in an internal posted write buffers and is subsequently delivered to the target. The ...
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If offset 74h bits [8:7] = 00, the PI7C8150A converts Memory Write and Invalidate transactions to Memory Write transactions at the destination. If the value in the cache line size register does meet the memory write and invalidate conditions, the ...
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PI7C8150A implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction completion queue. The initial value of this timer can be set to the retry counter register offset 78h. If ...
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READ TRANSACTIONS Delayed read forwarding is used for all read transactions crossing PI7C8150A. Delayed read transactions are treated as either prefetchable or non-prefetchable. Table 3-5 shows the read behavior, prefetchable or non-prefetchable, for each type of read operation. 3.6.1 ...
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READ PREFETCH ADDRESS BOUNDARIES PI7C8150A imposes internal read address boundaries on read pre-fetched data. When a read transaction reaches one of these aligned address boundaries, the PI7C8150A stops pre- fetched data, unless the target signals a target disconnect before ...
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When PI7C8150A accepts a delayed read request, it first samples the read address, read bus command, and address parity. When IRDY_L is asserted, PI7C8150A then samples the byte enable bits for the first data phase. This information is entered into ...
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When the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read ...
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Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type 0 configuration transaction is identified by the configuration command and the lowest two bits of the address set to ...
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Type 1 to Type 0 translations are performed only in the downstream direction; that is, PI7C8150A generates a Type 0 transaction only on the secondary bus, and never on the primary bus. PI7C8150A ...
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PI7C8150A can assert unique address lines to be used as IDSEL signals for devices on the secondary bus, for device numbers ranging from 0 through 8. Because of electrical loading constraints of the PCI ...
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The PI7C8150A forwards Type 1 to Type 1 configuration write transactions as delayed transactions. Type 1 to Type 1 configuration write transactions are limited to a single data transfer. 3.7.4 SPECIAL CYCLES The Type 1 configuration mechanism is used to ...
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Normal termination occurs when the initiator de-asserts FRAME_L at the beginning of the last data phase, and de-asserts IRDY# at the end of the last data phase in conjunction with either TRDY_L or STOP_L assertion from the target. Master abort ...
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For burst transfer, with the exception of “Memory Write and Invalidate” transactions, the master latency timer expires and the PI7C8150A’s bus grant is de-asserted. The target terminates the transaction with a retry, disconnect, or target abort. If PI7C8150A is delivering ...
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Target disconnect Target abort PI7C8150A handles these terminations in different ways, depending on the type of transaction being performed. 3.8.3.1 DELAYED WRITE TARGET TERMINATION RESPONSE When PI7C8150A initiates a delayed write transaction, the type of target termination received from the ...
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Table 3-8. Response to Posted Write Target Termination Target Termination Normal Target Retry Target Disconnect Target Abort Note that when a target retry or target disconnect is returned and posted write data associated with that transaction remains in the write ...
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Target Termination Target Abort After PI7C8150A makes 2 target bus, PI7C8150A asserts P_SERR_L if the primary SERR_L enable bit is set (bit 8 of command register for secondary bus) and the delayed-write-non-delivery bit is not set. The delayed-write-non-delivery bit is ...
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The delayed transaction queue is full, and the transaction cannot be queued. A delayed read request with the same address and bus command has already been queued. A locked sequence is being propagated across PI7C8150A, and the read transaction is ...
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When PI7C8150A returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface. 4 ADDRESS DECODING PI7C8150A uses three address ranges that control I/O and memory transaction forwarding. ...
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I/O enable bit is not set. To enable upstream forwarding of I/O transactions, the master enable bit must be set in the command register. If the master- enable bit is not set, PI7C8150A ignores all ...
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I/O enable bit or the master enable bit in the command register in configuration space. 4.2.2 ISA MODE PI7C8150A supports ISA mode by providing an ISA enable bit in the bridge control ...
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Configure the memory-mapped I/O base and limit address registers, prefetchable memory base and limit address registers, and VGA mode bit before setting the memory enable and master enable bits, and change them subsequently only when the ...
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PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS Locations accessed in the prefetchable memory address range must have true memory-like behavior and must not exhibit side effects when read. This means that extra reads to a prefetchable memory location must ...
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VGA SUPPORT PI7C8150A provides two modes for VGA support: VGA mode, supporting VGA-compatible addressing VGA snoop mode, supporting VGA palette forwarding 4.4.1 VGA MODE When a VGA-compatible device exists downstream from PI7C8150A, set the VGA mode bit in the ...
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TRANSACTION ORDERING To maintain data coherency and consistency, PI7C8150A complies with the ordering rules set forth in the PCI Local Bus Specification, Revision 2.3, for transactions crossing the bridge. This chapter describes the ordering rules that control transaction forwarding ...
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PI7C8150A does not merge bytes on separate masked write transactions to the same DWORD address—this optimization is also best implemented in the originating master. PI7C8150A does not collapse sequential write transactions to the same address into a single write transaction—the ...
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Table 5-1 shows the ordering relationships of all the transactions and refers by number to the ordering rules that follow. 06-0057 2-PORT PCI-TO-PCI BRIDGE Page 49 of 111 APRIL 2006 – Revision 1.1 PI7C8150A ...
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Table 5-1. Summary of Transaction Ordering Pass Posted Write Delayed Read Request Delayed Write Request Delayed Read Completion Delayed Write Completion Note: The superscript accompanying some of the table entries refers to any applicable ordering rule listed in this section. ...
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Table 5-1. These ordering rules apply to posted write transactions, delayed write and read requests, and delayed write and read completion transactions crossing PI7C8150A in the same direction. Note that delayed completion transactions cross PI7C8150A in the direction opposite that ...
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PI7C8150A does not have a hardware mechanism to guarantee data synchronization for posted write transactions. Therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written (or some other location ...
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If the parity error response bit is set in the bridge control register, PI7C8150A does not claim the transaction with S_DEVSEL_L; this may allow the transaction to terminate in a master abort. If parity error response bit is not set, ...
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PI7C8150A sets the detected parity error bit in the secondary status register. PI7C8150A sets the data parity detected bit in the secondary status register, if the secondary interface parity error response bit is set in the bridge control register. PI7C8150A ...
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When a delayed write transaction is normally queued, the address, command, address parity, data, byte enable bits, and data parity are all captured and a target retry is returned to the initiator. When PI7C8150A detects a parity error on the ...
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For downstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C8150A has write status to return, the following events occur: PI7C8150A first asserts P_TRDY_L and then asserts P_PERR_L two cycles later, if the primary ...
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PI7C8150A completes the transaction normally. 6.2.4 POSTED WRITE TRANSACTIONS During downstream posted write transactions, when PI7C8150A responds as a target, it detects a data parity error on the initiator (primary) bus and the following events occur: PI7C8150A asserts P_PERR_L two ...
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During upstream write transactions, when a data parity error is reported on the target (primary) bus by the target’s assertion of P_PERR_L, the following events occur: PI7C8150A sets the data parity detected bit in the status register, if the parity ...
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X = don’t care Table 6-2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. This bit is set when PI7C8150A detects a parity error on the secondary interface. Table 6-2. Setting ...
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The PI7C8150A must be a master on the secondary bus. The parity error response bit must be set in the bridge control register of secondary interface. The S_PERR_L signal is detected asserted or a parity error is detected on the ...
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X = don’t care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. Table 6-6 shows assertion of S_PERR_L that is set under the following conditions: PI7C8150A is either the target ...
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P_SERR_L (asserted don’t care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. 3 The parity error was ...
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Master timeout on delayed transaction The device-specific P_SERR_L status register reports the reason for the assertion of P_SERR_L. Most of these events have additional device-specific disable bits in the P_SERR_L event disable register that make it possible to mask out ...
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Because a target retry is signaled to the initiator, the initiator must relinquish the lock on the ...
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Memory Write induces master abort When PI7C8150A receives a target abort or a master abort in response to the delayed locked read transaction, this status is passed back to the initiator, and no locks are established on either the target ...
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SERR_L enable bit is set in the command register. Signal SERR_L is asserted for the master abort condition if the master abort mode bit is set in the bridge control register (see Section ...
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The secondary bus request and grant signals are connected internally to the arbiter and are not brought out to external pins when S_CFN_L is HIGH. Figure 8-1 The secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with each set ...
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If PI7C8150A detects that an initiator has failed to assert S_FRAME_L after 16 cycles of both grant assertion and a secondary idle bus condition, the arbiter de-asserts the grant. To prevent bus contention, if the secondary PCI bus is idle, ...
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PI7C8150A can start the transaction on the next PCI clock cycle by asserting P_FRAME_L if P_GNT_L is still asserted. If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last master that used the ...
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GPIO CONTROL REGISTERS During normal operation, the following device specific configuration registers control the GPIO interface: The GPIO output data register The GPIO output enable control register The GPIO input data register These registers consist of five 8-bit fields: ...
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An external shift register should be used to load and shift the data. The GPIO pins are used for shift register control and serial data input. Table 10-1 shows the operation of the GPIO pins. Table 10-1. GPIO Operation GPIO ...
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The next bit is tied LOW because that secondary clock output is connected to the PI7C8150A S_CLKIN input. When the secondary reset signal, S_RST_L, is detected asserted and the primary reset signal, P_RST_L, is detected deasserted, PI7C8150A ...
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Support of the B2 secondary bus power state when in the D3 state Table 11-1 shows the states and related actions that PI7C8150A performs during power management transitions. (No other transactions are permitted.) Table 11-1. Power Management Transitions Current Status ...
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SECONDARY INTERFACE RESET PI7C8150A is responsible for driving the secondary bus reset signals, S_RESET_L. PI7C8150A asserts S_RESET_L when any of the following conditions are met: Signal P_RESET_L is asserted. Signal S_RESET_L remains asserted as long as P_RESET_L is asserted ...
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P_CBE [3:0] 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 06-0057 2-PORT PCI-TO-PCI BRIDGE Command Action Special Cycle Do not claim. Ignore. I/O Read 1. If address is within pass through I/O range, claim ...
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P_CBE [3:0] 1111 13.2 SECONDARY INTERFACE S_CBE[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 06-0057 2-PORT PCI-TO-PCI BRIDGE Command Action Memory Write and Same as Memory Read Invalidate Command Action Interrupt ...
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CONFIGURATION REGISTERS PCI configuration defines a 64-byte space (configuration header) to define various attributes of PI7C8150A as shown below. 14.1 CONFIGURATION REGISTER 31-24 Reserved Secondary Latency Timer Secondary Status Prefetchable Memory Limit I/O Limit Upper 16-bit Upstream Memory Control ...
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VENDOR ID REGISTER – OFFSET 00h Bit Function 15:0 Vendor ID 14.1.2 DEVICE ID REGISTER – OFFSET 00h Bit Function 31:16 Device ID 14.1.3 COMMAND REGISTER – OFFSET 04h Bit Function 0 I/O Space Enable Memory Space 1 Enable ...
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Bit Function Parity Error 6 Response Wait Cycle 7 Control P_SERR_L 8 enable Fast Back-to- 9 Back Enable 15:10 Reserved 14.1.4 STATUS REGISTER – OFFSET 04h Bit Function 19:16 Reserved 20 Capabilities List 21 66MHz Capable 22 Reserved 23 Fast ...
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Bit Function 27 Signaled Target Abort 28 Received Target Abort 29 Received Master Abort 30 Signaled System Error 31 Detected Parity Error 14.1.5 REVISION ID REGISTER – OFFSET 08h Bit Function 7:0 Revision 14.1.6 CLASS CODE REGISTER – OFFSET 08h ...
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HEADER TYPE REGISTER – OFFSET 0Ch Bit Function 23:16 Header Type 14.1.10 PRIMARY BUS NUMBER REGISTSER – OFFSET 18h Bit Function 7:0 Primary Bus Number 14.1.11 SECONDARY BUS NUMBER REGISTER – OFFSET 18h Bit Function 15:8 Secondary Bus Number ...
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Bit Function 7:4 I/O Base Address [15:12] 14.1.15 I/O LIMIT REGISTER – OFFSET 1Ch Bit Function 11:8 32-bit Indicator 15:12 I/O Base Address [15:12] 14.1.16 SECONDARY STATUS REGISTER – OFFSET 1Ch Bit Function 20:16 Reserved 21 66MHz Capable 22 Reserved ...
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Bit Function Received Master 29 Abort Received System 30 Error Detected Parity 31 Error 14.1.17 MEMORY BASE REGISTER – OFFSET 20h Bit Function 3:0 15:4 Memory Base Address [15:4] 14.1.18 MEMORY LIMIT REGISTER – OFFSET 20h Bit Function 19:16 31:20 ...
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PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h Bit Function 19:16 64-bit addressing 31:20 Prefetchable Memory Limit Address [31:20] 14.1.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h Bit Function 31:0 Prefetchable Memory Base Address, Upper 32-bits [63:32] ...
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I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h Bit Function 31:0 I/O Limit Address, Upper 16-bits [31:16] 14.1.25 ECP POINTER REGISTER – OFFSET 34h Bit Function 7:0 Enhanced Capabilities Port Pointer 14.1.26 INTERRUPT LINE REGISTER – OFFSET 3Ch ...
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Bit Function 18 ISA enable 19 VGA enable 20 Reserved 21 Master Abort Mode 22 Secondary Interface Reset 23 Fast Back-to- Back Enable 24 Primary Master Timeout 06-0057 2-PORT PCI-TO-PCI BRIDGE Type Description R/W Modifies the bridge’s response to ISA ...
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Bit Function 25 Secondary Master Timeout 26 Master Timeout Status 27 Discard Timer P_SERR_L enable 31-28 Reserved 14.1.29 DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h Bit Function 0 Reserved 1 Memory Write Disconnect Control 3:2 Reserved 4 Secondary Bus ...
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Bit Function 10:9 Test Mode For All Counters at P and S1 15:11 Reserved 14.1.30 ARBITER CONTROL REGISTER – OFFSET 40h Bit Function 24:16 Arbiter Control 25 Priority of Secondary Interface 31:26 Reserved 14.1.31 EXTENDED CHIP CONTROL REGISTER – OFFSET ...
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UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h Bit Function Upstream ( Memory Base and Limit Enable 31:17 Reserved 14.1.33 SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET 4Ch Bit Function Secondary bus arbiter 31:28 preemption control ...
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UPSTREAM ( MEMORY LIMIT REGISTER – OFFSET 50h Bit Function 19:16 64 bit addressing Upstream 31:20 Memory Limit Address 14.1.36 UPSTREAM ( MEMORY BASE UPPER 32-BITS REGISTER – OFFSET 54h Bit Function Upstream 31:0 Memory ...
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Bit Function Target Abort 3 During Posted Write Master Abort On 4 Posted Write Delayed Write 5 Non-Delivery Delayed Read – Data From Target 7 Reserved 14.1.39 GPIO DATA AND CONTROL REGISTER – OFFSET 64h Bit Function GPIO ...
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Bit Function GPIO Output 19:16 Enable Write-1- to-Clear GPIO Output Enable Write-1- 23:20 to-Set 27:24 Reserved GPIO Input Data 31:28 Register 14.1.40 SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h Bit Function 1:0 Clock 0 disable 3:2 Clock 1 disable 5:4 ...
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Bit Function Target Abort 19 during Posted Write Master Abort 20 during Posted Write Delayed Write 21 Non-delivery Delayed Read – Data from Target Delayed 23 Transaction Master Timeout 14.1.42 PORT OPTION REGISTER – OFFSET 74h Bit Function ...
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Bit Function Secondary MEMW 4 Command Alias Enable 5:6 Reserved Primary MEMWI 7 Command Alias Enable Secondary MEMWI 8 Command Alias Enable Enable Long 9 Request Enable Secondary To 10 Hold Request Longer Enable Primary 11 To Hold Request Longer ...
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RETRY COUNTER REGISTER – OFFSET 78h Bit Function 31:0 Retry Counter 14.1.44 PRIMARY MASTER TIMEOUT COUNTER – OFFSET 80h Bit Function 15:0 Primary Timeout 14.1.45 SECONDARY MASTER TIMEOUT COUNTER – OFFSET 80h Bit Function Secondary 31:16 Timeout 14.1.46 CAPABILITY ...
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SLOT NUMBER REGISTER – OFFSET B0h Bit Function Expansion Slot 20:16 Number 21 First in Chassis 23:22 Reserved 14.1.49 CHASSIS NUMBER REGISTER – OFFSET B0h Bit Function Chassis Number 31:24 Register 14.1.50 CAPABILITY ID REGISTER – OFFSET DCh Bit ...
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POWER MANAGEMENT DATA REGISTER – OFFSET E0h Bit Function 1:0 Power State 7:2 Reserved 8 PME# Enable 12:9 Data Select 14:13 Data Scale 15 PME status 14.1.54 CAPABILITY ID REGISTER – OFFSET E4h Bit Function 7:0 Capability ID 14.1.55 ...
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BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES Initiator Master on Primary Master on Primary Master on Primary Master on Secondary Master on Secondary Master on Secondary 15.2 ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER) 15.2.1 MASTER ABORT Master abort indicates that ...
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REPORTING PARITY ERRORS For all address phases parity error is detected, the error should be reported on the P_SERR_L signal by asserting P_SERR_L for one cycle and then 3-stating two cycles after the bad address. P_SERR_L can ...
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This mode of operation is valuable for design debugging and fault diagnosis since it permits examination of connections not normally accessible to the test system. The following subsections describe the boundary-scan test logic elements: TAP pins, instruction register, test data ...
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The instruction determines the test to be performed, the test data register to be accessed, or both. The IR is two bits wide. When the IR is selected, the most significant bit is connected to TDI, and the least significant ...
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TAP TEST DATA REGISTERS The PI7C8150A contains two test data registers (bypass and boundary-scan). Each test data register selected by the TAP controller is connected serially between TDI and TDO. TDI is connected to the test data register’s most ...
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TCK. The value of the test mode state (TMS) input signal at a rising edge of TCK controls the sequence of state changes. The TAP controller is initialized after power-up by applying a low to the TRST_L pin. In addition, ...
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Boundary-Scan Register Number ...
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Boundary-Scan Register Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 06-0057 2-PORT ...
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ELECTRICAL AND TIMING SPECIFICATIONS 17.1 MAXIMUM RATINGS (Above which the useful life may be impaired. For user guidelines, not tested). Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground Potentials (AV Voltage at Input Pins Note: Stresses ...
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AC SPECIFICATIONS Figure 17-1 Symbol Parameter Tsu Input setup time to CLK – bused signals Tsu(ptp) Input setup time to CLK – point-to-point Th Input signal hold time from CLK Tval CLK to signal valid delay – bused signals ...
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TIMING 17.4 Symbol Parameter T SKEW among S_CLKOUT[9:0] SKEW T DELAY between PCLK and S_CLKOUT[9:0] DELAY T P_CLK, S_CLKOUT[9:0] cycle time CYCLE T P_CLK, S_CLKOUT[9:0] HIGH time HIGH T P_CLK, S_CLKOUT[9:0] LOW time LOW 17.5 33MHZ TIMING Symbol Parameter ...
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PACKAGE INFORMATION 18.1 208-PIN FQFP PACKAGE DIAGRAM Figure 18-1 06-0057 2-PORT PCI-TO-PCI BRIDGE 208-pin FQFP Package Outline Page 109 of 111 APRIL 2006 – Revision 1.1 PI7C8150A ...
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... Thermal characteristics can be found on the web: 18.3 PART NUMBER ORDERING INFORMATION Part Number PI7C8150AMA PI7C8150AND PI7C8150AMA-33 PI7C8150AND-33 PI7C8150AMAE PI7C8150ANDE PI7C8150AMAE-33 06-0057 2-PORT PCI-TO-PCI BRIDGE 256-pin PBGA Package Outline http://www.pericom.com/packaging/mechanicals.php Speed Pin – Package 66MHz 208 – FQFP 66MHz 256 – PBGA 33MHz 208 – ...
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PCI-TO-PCI BRIDGE NOTES: Page 111 of 111 APRIL 2006 – Revision 1.1 PI7C8150A ...