PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet - Page 28

• Manufacturer Part Number: PI7C8150AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
3.6.3
3.6.4
Table 3-4. Read Prefetch Address Boundaries
Table 3-5. Read Transaction Prefetching
READ PREFETCH ADDRESS BOUNDARIES
PI7C8150A imposes internal read address boundaries on read pre-fetched data. When a
read transaction reaches one of these aligned address boundaries, the PI7C8150A stops pre-
fetched data, unless the target signals a target disconnect before the read pre-fetched
boundary is reached. When PI7C8150A finishes transferring this read data to the initiator,
it returns a target disconnect with the last data transfer, unless the initiator completes the
transaction before all pre-fetched read data is delivered. Any leftover pre-fetched data is
discarded.
Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB
address boundary, or until the initiator de-asserts FRAME_L. Section 3.6.6 describes flow-
through mode during read operations.
Table 3-4 shows the read pre-fetch address boundaries for read transactions during non-
flow-through mode.
DELAYED READ REQUESTS
PI7C8150A treats all read transactions as delayed read transactions, which means that the
read request from the initiator is posted into a delayed transaction queue. Read data from
the target is placed in the read data queue directed toward the initiator bus interface and is
transferred to the initiator when the initiator repeats the read transaction.
- does not matter if it is prefetchable or non-prefetchable
* don’t care
See Section 4.3 for detailed information about prefetchable and non-prefetchable address spaces.
Type of Transaction
Configuration Read
I/O Read
Memory Read
Memory Read
Memory Read
Memory Read Line
Memory Read Line
Memory Read Multiple
Memory Read Multiple
Type of Transaction
I/O Read
Configuration Read
Memory Read
Memory Read Line
Memory Read Multiple
Address Space
-
-
Non-Prefetchable
Prefetchable
Prefetchable
-
-
-
-
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Read Behavior
Prefetching never allowed
Prefetching never allowed
Downstream: Prefetching used if address is prefetchable space
Upstream: Prefetching used or programmable
Prefetching always used
Prefetching always used
Cache
(CLS)
*
CLS = 1, 2, 4, 8, 16
*
*
CLS = 0 or 16
CLS = 1, 2, 4, 8, 16
CLS = 0 or 16
CLS = 1, 2, 4, 8, 16
CLS = 0 or 16
Line
2-PORT PCI-TO-PCI BRIDGE
Size
APRIL 2006 – Revision 1.1
Prefetch
Boundary
One DWORD (no prefetch)
One DWORD (no prefetch)
One DWORD (no prefetch)
16-DWORD aligned address
boundary
Cache line address boundary
16-DWORD aligned address
boundary
Cache line boundary
32-DWORD aligned address
boundary
2X of cache line boundary
Aligned
PI7C8150A
Address