PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet - Page 71

• Manufacturer Part Number: PI7C8150AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
Table 10-1. GPIO Operation
Table 10-2. GPIO Serial Data Format
An external shift register should be used to load and shift the data. The GPIO pins are used
for shift register control and serial data input. Table 10-1 shows the operation of the GPIO
pins.
The data is input through the dedicated input signal, MSK_IN.
The shift register circuitry is not necessary for correct operation of PI7C8150A. The shift
register can be eliminated, and MSK_IN can be tied LOW to enable all secondary clock
outputs or tied HIGH to force all secondary clock outputs HIGH. Table 10-2 shows the
format of the serial stream.
The first 8 bits contain the PRSNT#[1:0] signal values for four slots, and these bits control
the S_CLKOUT[3:0] outputs. If one or both of the PRSNT#[1:0] signals are 0, that
indicates that a card is present in the slot and therefore the secondary clock for that slot is
not masked. If these clocks are connected to devices and not to slots, one or both of the bits
should be tied low to enable the clock.
The next 5 bits are the clock mask for devices; each bit enables or disables the clock for
one device. These bits control the S_CLKOUT[8:4] outputs: 0 enables the clock, and 1
disables the clock.
Bit 13 is the clock enable bit for S_CLKOUT[9], which is connected to PI7C8150A’s
S_CLKIN input.
If desired, the assignment of S_CLKOUT outputs to slots, devices, and PI7C8150A’s
S_CLKIN input can be rearranged from the assignment shown here. However, it is
important that the serial data stream format match the assignment of S_CLKOUT.
The 8 least significant bits are connected to the PRSNT# pins for the slots. The next 5 bits
are tied high to disable their respective secondary clocks because those clocks are not
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
[1:0]
[3:2]
[5:4]
[7:6]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Bit
GPIO Pin
Slot 0 PRSNT#[1:0] or device 0
Slot 1 PRSNT#[1:0] or device 1
Slot 2 PRSNT#[1:0] or device 2
Slot 3 PRSNT#[1:0] or device 3
Device 4
Device 5
Device 6
Device 7
Device 8
PI7C8150A S_CLKIN
Reserved
Reserved
Page 71 of 111
Description
Shift register clock output at 33MHz max frequency
Not used
Shift register control
0: Load
1: Shift
Not used
2-PORT PCI-TO-PCI BRIDGE
Operation
APRIL 2006 – Revision 1.1
0
1
2
3
4
5
6
7
8
9
NA
NA
S_CLKOUT
PI7C8150A