PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet - Page 82

• Manufacturer Part Number: PI7C8150AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
14.1.15
14.1.16
I/O LIMIT REGISTER – OFFSET 1Ch
SECONDARY STATUS REGISTER – OFFSET 1Ch
Bit
7:4
Bit
11:8
15:12
Bit
20:16
21
22
23
24
26:25
27
28
Function
I/O Base Address
[15:12]
Function
32-bit Indicator
I/O Base Address
[15:12]
Function
Reserved
66MHz Capable
Reserved
Fast Back-to-
Back Capable
Master Data
Parity Error
Detected
DEVSEL_L
timing
Signaled Target
Abort
Received Target
Abort
Type
R/W
Type
R/O
R/W
Type
R/O
R/O
R/O
R/O
R/WC
R/O
R/WC
R/WC
Page 82 of 111
Description
Defines the bottom address of the I/O address range for the bridge
to determine when to forward I/O transactions from one interface to
the other. The upper 4 bits correspond to address bits [15:12] and
are writable. The lower 12 bits corresponding to address bits [11:0]
are assumed to be 0. The upper 16 bits corresponding to address
bits [31:16] are defined in the I/O base address upper 16 bits address
register
Reset to 0
Description
Read as 01h to indicate 32-bit I/O addressing
Defines the top address of the I/O address range for the bridge to
determine when to forward I/O transactions from one interface to
the other. The upper 4 bits correspond to address bits [15:12] and
are writable. The lower 12 bits corresponding to address bits [11:0]
are assumed to be FFFh. The upper 16 bits corresponding to
address bits [31:16] are defined in the I/O base address upper 16 bits
address register
Reset to 0
Description
Reset to 0
Set to 1 to enable 66MHz operation on the secondary interface
Reset to 1
Reset to 0
Set to 1 to enable decoding of fast back-to-back transactions on the
secondary interface to different targets
Reset to 0
Set to 1 when S_PERR_L is asserted and bit 6 of command register
is set
Reset to 0
DEVSEL# timing (medium decoding)
00: fast DEVSEL_L decoding
01: medium DEVSEL_L decoding
10: slow DEVSEL_L decoding
11: reserved
Reset to 01
Set to 1 (by a target device) whenever a target abort cycle occurs on
its secondary interface
Reset to 0
Set to 1 (by a master device) whenever transactions on its secondary
interface are terminated with target abort
Reset to 0
2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 1.1
PI7C8150A