PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet - Page 72

• Manufacturer Part Number: PI7C8150AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
10.3
11
connected to anything. The next bit is tied LOW because that secondary clock output is
connected to the PI7C8150A S_CLKIN input. When the secondary reset signal, S_RST_L,
is detected asserted and the primary reset signal, P_RST_L, is detected deasserted,
PI7C8150A drives GPIO[2] LOW for one cycle to load the clock mask inputs into the shift
register. On the next cycle, PI7C8150A drives GPIO[2] HIGH to perform a shift operation.
This shifts the clock mask into MSK_IN; the most significant bit is shifted in first, and the
least significant bit is shifted in last.
After the shift operation is complete, PI7C8150A tri-states the GPIO signals and can
deassert S_RST_L if the secondary reset bit is clear. PI7C8150A then ignores MSK_IN.
Control of the GPIO signal now reverts to PI7C8150A GPIO control registers. The clock
disable mask can be modified subsequently through a configuration write command to the
secondary clock control register in device-specific configuration space.
LIVE INSERTION
The GPIO[3] pin can be used, along with a live insertion mode bit, to disable transaction
forwarding.
To enable live insertion mode, the live insertion mode bit in the chip control register must
be set to 1, and the output enable control for GPIO[3] must be set to input only in the GPIO
output enable control register. When live insertion mode is enabled, whenever GPIO[3] is
driven to a value of 1, the I/O enable, the memory enable, and the master enable bits are
internally masked to 0. This means that, as a target, PI7C8150A no longer accepts any I/O
or memory transactions, on either interface. When read, the register bits still reflect the
value originally written by a configuration write command; when GPIO[3] is deasserted,
the internal enable bits return to their original value (as they appear when read from the
command register). When this mode is enabled, as a master, PI7C8150A completes any
posted write or delayed request transactions that have already been queued.
Delayed completion transactions are not returned to the master in this mode because
PI7C8150A is not responding to any I/O or memory transactions during this time.
PI7C8150A continues to accept configuration transactions in live insertion mode. Once live
insertion mode brings PI7C8150A to a halt and queued transactions are completed, the
secondary reset bit in the bridge control register can be used to assert S_RST_L, if desired,
to reset and tri-state secondary bus devices, and to enable any live insertion hardware.
PCI POWER MANAGEMENT
PI7C8150A incorporates functionality that meets the requirements of the PCI Power
Management Specification, Revision 1.0. These features include:
PCI Power Management registers using the Enhanced Capabilities Port (ECP) address
mechanism
Support for D0, D3
Support for D0, D1, D2, D3
behind the bridge
hot
and D3
Page 72 of 111
hot
cold
, and D3
power management states
cold
power management states for devices
2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 1.1
PI7C8150A