PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet - Page 8

• Manufacturer Part Number: PI7C8150AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
15
16
17
15.1
15.2
16.1
16.2
16.3
16.4
16.5
16.6
17.1
17.2
17.3
17.4
17.5
17.6
14.1.33
4Ch
14.1.34
14.1.35
14.1.36
14.1.37
58h
14.1.38
14.1.39
14.1.40
14.1.41
14.1.42
14.1.43
14.1.44
14.1.45
14.1.46
14.1.47
14.1.48
14.1.49
14.1.50
14.1.51
14.1.52
14.1.53
14.1.54
14.1.55
15.2.1
15.2.2
15.2.3
15.2.4
16.1.1
16.1.2
BRIDGE BEHAVIOR .......................................................................................... 97
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ..................................... 99
ELECTRICAL AND TIMING SPECIFICATIONS....................................... 106
AC SPECIFICATIONS.............................................................................................................. 107
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES........................................................... 98
ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER)................................ 98
BOUNDARY SCAN ARCHITECTURE................................................................................. 99
BOUNDARY SCAN INSTRUCTION SET .......................................................................... 101
TAP TEST DATA REGISTERS............................................................................................ 102
BYPASS REGISTER ............................................................................................................. 102
BOUNDARY-SCAN REGISTER.......................................................................................... 102
TAP CONTROLLER ............................................................................................................. 102
MAXIMUM RATINGS ......................................................................................................... 106
DC SPECIFICATIONS .......................................................................................................... 106
66MHZ TIMING.................................................................................................................... 108
33MHZ TIMING.................................................................................................................... 108
POWER CONSUMPTION .................................................................................................... 108
MASTER ABORT................................................................................................................ 98
PARITY AND ERROR REPORTING ................................................................................ 98
REPORTING PARITY ERRORS ....................................................................................... 99
SECONDARY IDSEL MAPPING ...................................................................................... 99
TAP PINS .......................................................................................................................... 100
INSTRUCTION REGISTER ............................................................................................ 100
SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET
UPSTREAM (S TO P) MEMORY BASE REGISTER – OFFSET 50h ........................ 89
UPSTREAM (S TO P) MEMORY LIMIT REGISTER – OFFSET 50h....................... 90
UPSTREAM (S TO P) MEMORY BASE UPPER 32-BITS REGISTER – OFFSET 54h
UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS REGISTER – OFFSET
P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h........................................ 90
GPIO DATA AND CONTROL REGISTER – OFFSET 64h ........................................ 91
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h ................................. 92
P_SERR_L STATUS REGISTER – OFFSET 68h ........................................................ 92
PORT OPTION REGISTER – OFFSET 74h ................................................................ 93
RETRY COUNTER REGISTER – OFFSET 78h .......................................................... 95
PRIMARY MASTER TIMEOUT COUNTER – OFFSET 80h ..................................... 95
SECONDARY MASTER TIMEOUT COUNTER – OFFSET 80h ............................... 95
CAPABILITY ID REGISTER – OFFSET B0h ............................................................. 95
NEXT POINTER REGISTER – OFFSET B0h ............................................................. 95
SLOT NUMBER REGISTER – OFFSET B0h .............................................................. 96
CHASSIS NUMBER REGISTER – OFFSET B0h ....................................................... 96
CAPABILITY ID REGISTER – OFFSET DCh............................................................. 96
NEXT ITEM POINTER REGISTER – OFFSET DCh ................................................. 96
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DCh ................. 96
POWER MANAGEMENT DATA REGISTER – OFFSET E0h................................... 97
CAPABILITY ID REGISTER – OFFSET E4h ............................................................. 97
NEXT POINTER REGISTER – OFFSET E4h ............................................................. 97
.......................................................................................................................................... 89
.......................................................................................................................................... 90
.......................................................................................................................................... 90
Page 8 of 111
2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 1.1
PI7C8150A