PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet - Page 94

• Manufacturer Part Number: PI7C8150AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
Bit
4
5:6
7
8
9
10
11
15:12
Function
Secondary
MEMW
Command Alias
Enable
Reserved
Primary
MEMWI
Command Alias
Enable
Secondary
MEMWI
Command Alias
Enable
Enable Long
Request
Enable
Secondary To
Hold Request
Longer
Enable Primary
To Hold Request
Longer
Reserved
Type
R/W
R/O
R/W
R/W
R/W
R/W
R/W
R/O
Page 94 of 111
Description
Controls PI7C8150A’s detection mechanism for matching non-posted
memory write retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the secondary interface
1: alias MEMWI to MEMW for non-posted memory write retry
cycles from initiator on the secondary interface
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
Controls PI7C8150A’s detection mechanism for matching non-posted
memory write and invalidate cycles from the initiator on the primary
interface
0: When accepting MEMWI command at the primary interface,
PI7C8150A converts MEMWI to MEMW command on the
secondary interface
1: Disconnects MEMWI command at aligned cache line boundaries
Controls PI7C8150A’s detection mechanism for matching non-posted
memory write and invalidate cycles from the initiator on the
secondary interface
0: When accepting MEMWI command at the secondary interface,
PI7C8150A converts MEMWI to MEMW command on the primary
interface
1: Disconnects MEMWI command at aligned cache line boundaries
Controls PI7C8150A’s ability to enable long requests for lock cycles
0: normal lock operation
1: enable long request for lock cycle
Reset to 0
Controls PI7C8150A’s ability to enable the secondary bus to hold
requests longer.
0: internal secondary master will release REQ_L after FRAME_L
assertion
1: internal secondary master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
Controls PI7C8150A’s ability to hold requests longer at the Primary
Port.
0: internal Primary master will release REQ_L after FRAME_L
assertion
1: internal Primary master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
Reserved. Returns 0 when read. Reset to 0.
2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 1.1
PI7C8150A