PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet - Page 51

• Manufacturer Part Number: PI7C8150AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
5.4
Table 5-1. These ordering rules apply to posted write transactions, delayed write and read
requests, and delayed write and read completion transactions crossing PI7C8150A in the
same direction. Note that delayed completion transactions cross PI7C8150A in the
direction opposite that of the corresponding delayed requests.
1. Posted write transactions must complete on the target bus in the order in which they
were received on the initiator bus. The subsequent posted write transaction can be setting a
flag that covers the data in the first posted write transaction; if the second transaction were
to complete before the first transaction, a device checking the flag could subsequently
consume stale data.
2. A delayed read request traveling in the same direction as a previously queued posted
write transaction must push the posted write data ahead of it. The posted write transaction
must complete on the target bus before the delayed read request can be attempted on the
target bus. The read transaction can be to the same location as the write data, so if the read
transaction were to pass the write transaction, it would return stale data.
3. A delayed read completion must ‘‘pull’’ ahead of previously queued posted write data
traveling in the same direction. In this case, the read data is traveling in the same direction
as the write data, and the initiator of the read transaction is on the same side of PI7C8150A
as the target of the write transaction. The posted write transaction must complete to the
target before the read data is returned to the initiator. The read transaction can be a reading
to a status register of the initiator of the posted write data and therefore should not
complete until the write transaction is complete.
4. Delayed write requests cannot pass previously queued posted write data. For posted
memory write transactions, the delayed write transaction can set a flag that covers the data
in the posted write transaction. If the delayed write request were to complete before the
earlier posted write transaction, a device checking the flag could subsequently consume
stale data.
5. Posted write transactions must be given opportunities to pass delayed read and write
requests and completions. Otherwise, deadlocks may occur when some bridges which
support delayed transactions and other bridges which do not support delayed transactions
are being used in the same system. A fairness algorithm is used to arbitrate between the
posted write queue and the delayed transaction queue.
DATA SYNCHRONIZATION
Data synchronization refers to the relationship between interrupt signaling and data
delivery. The PCI Local Bus Specification, Revision 2.3, provides the following alternative
methods for synchronizing data and interrupts:
The device signaling the interrupt performs a read of the data just written (software).
The device driver performs a read operation to any register in the interrupting device
before accessing data written by the device (software).
System hardware guarantees that write buffers are flushed before interrupts are
forwarded.
Page 51 of 111
2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 1.1
PI7C8150A