PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet - Page 39

• Manufacturer Part Number: PI7C8150AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
3.8.4
3.8.4.1
After PI7C8150A makes 2
target bus, PI7C8150A asserts P_SERR_L if the primary SERR_L enable bit is set (bit 8 of
command register for secondary bus) and the delayed-write-non-delivery bit is not set. The
delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register (offset 64h).
PI7C8150A will report system error. See Section 6.4 for a description of system error
conditions.
TARGET TERMINATION INITIATED BY PI7C8150A
PI7C8150A can return a target retry, target disconnect, or target abort to an initiator for
reasons other than detection of that condition at the target interface.
TARGET RETRY
PI7C8150A returns a target retry to the initiator when it cannot accept write data or return
read data as a result of internal conditions. PI7C8150A returns a target retry to an initiator
when any of the following conditions is met:
For delayed write transactions:
For delayed read transactions:
Target Termination
Target Abort
The transaction is being entered into the delayed transaction queue.
Transaction has already been entered into delayed transaction queue, but target
response has not yet been received.
Target response has been received but has not progressed to the head of the return
queue.
The delayed transaction queue is full, and the transaction cannot be queued.
A transaction with the same address and command has been queued.
A locked sequence is being propagated across PI7C8150A, and the write transaction is
not a locked transaction.
The target bus is locked and the write transaction is a locked transaction.
Use more than 16 clocks to accept this transaction.
The transaction is being entered into the delayed transaction queue.
The read request has already been queued, but read data is not yet available.
Data has been read from target, but it is not yet at head of the read data queue or a
posted write transaction precedes it.
Response
Return target abort to initiator. Set received target abort bit in the target
interface status register. Set signaled target abort bit in the initiator interface
status register.
24
(default) attempts of the same delayed read transaction on the
Page 39 of 111
2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 1.1
PI7C8150A