PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet - Page 83

• Manufacturer Part Number: PI7C8150AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
14.1.17
14.1.18
14.1.19
MEMORY BASE REGISTER – OFFSET 20h
MEMORY LIMIT REGISTER – OFFSET 20h
PEFETCHABLE MEMORY BASE REGISTER – OFFSET 24h
Bit
29
30
31
Bit
3:0
15:4
Bit
19:16
31:20
Bit
3:0
15:4
Function
Received Master
Abort
Received System
Error
Detected Parity
Error
Function
Memory Base
Address [15:4]
Function
Memory Limit
Address [31:20]
Function
64-bit addressing
Prefetchable
Memory Base
Address [31:20]
Type
R/WC
R/WC
R/WC
Type
R/O
R/W
Type
R/O
R/W
Type
R/O
R/W
Page 83 of 111
Description
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 1
Defines the bottom address of an address range for the bridge to
determine when to forward memory read and write transactions from
one interface to the other. The upper 12 bits correspond to address
bits [31:20] and are writable. The lower 20 bits are assumed to be 0.
Description
Set to 1 (by a master) when transactions on its secondary interface
are terminated with Master Abort
Reset to 0
Set to 1 when S_SERR_L is asserted
Reset to 0
Set to 1 when address or data parity error is detected on the
secondary interface
Reset to 0
Description
Lower four bits of register are read only and return 0.
Reset to 0
Defines the bottom address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be 0.
Reset to 0
Description
Lower four bits of register are read only and return 0.
Reset to 0
Defines the top address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be FFFFFh.
2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 1.1
PI7C8150A