PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet - Page 61

• Manufacturer Part Number: PI7C8150AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
Table 6-6. Assertion of S_PERR_L
Table 6-7. Assertion of P_SERR_L for Data Parity Errors
2
Table 6-6 shows assertion of S_PERR_L that is set under the following conditions:
2
Table 6-7 shows assertion of P_SERR_L. This signal is set under the following conditions:
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
X = don’t care
S_PERR_L
1 (de-asserted)
0 (asserted)
1
1
1
1
1
0
1
1
0
0
X = don’t care
P_SERR_L
1 (de-asserted)
1
1
2
PI7C8150A is either the target of a write transaction or the initiator of a read
transaction on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
PI7C8150A detects a data parity error on the secondary bus or detects P_PERR_L
asserted during the completion phase of an upstream delayed write transaction on the
target (primary) bus.
PI7C8150A has detected P_PERR_L asserted on an upstream posted write transaction
or S_PERR_L asserted on a downstream posted write transaction.
PI7C8150A did not detect the parity error as a target of the posted write transaction.
The parity error response bit on the command register and the parity error response bit
on the bridge control register must both be set.
The SERR_L enable bit must be set in the command register.
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
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Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Direction
Downstream
Downstream
Upstream
Primary
Secondary
Secondary
Secondary
Secondary
Primary
Secondary
Primary
Primary
Primary
Primary
Secondary
Primary
Secondary
Primary
Bus Where Error
Bus Where Error
2-PORT PCI-TO-PCI BRIDGE
Was Detected
Was Detected
APRIL 2006 – Revision 1.1
x / x
x / 1
x / x
x / x
x / x
x / x
x / x
x / 1
x / x
x / x
1 / 1
x / 1
x / x
x / x
x / x
Secondary Parity
Secondary Parity
Error Response
Error Response
Primary /
Primary/
PI7C8150A
Bits
Bits