PI7C8150AMAE Pericom Semiconductor, PI7C8150AMAE Datasheet - Page 60

• Manufacturer Part Number: PI7C8150AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 208-FQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 208-FQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
Table 6-4. Setting Secondary Interface Master Data Parity Error Detected Bit
Table 6-5. Assertion of P_PERR_L
Table 6-5 shows assertion of P_PERR_L. This signal is set under the following conditions:
Secondary
Detected
Detected Bit
0
1
0
0
0
1
0
0
0
1
0
0
X= don’t care
P_PERR_L
1 (de-asserted)
1
0 (asserted)
1
0
1
1
1
0
0
1
1
2
The PI7C8150A must be a master on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
The S_PERR_L signal is detected asserted or a parity error is detected on the
secondary bus.
PI7C8150A is either the target of a write transaction or the initiator of a read
transaction on the primary bus.
The parity-error-response bit must be set in the command register of primary interface.
PI7C8150A detects a data parity error on the primary bus or detects S_PERR_L
asserted during the completion phase of a downstream delayed write transaction on the
target (secondary) bus.
Parity
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
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Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Secondary
Secondary
Secondary
Secondary
Primary
Secondary
Primary
Secondary
Secondary
Secondary
Secondary
Primary
Primary
Primary
Primary
Primary
Secondary
Primary
Secondary
Primary
Primary
Primary
Primary
Secondary
Bus Where Error
Bus Where Error
2-PORT PCI-TO-PCI BRIDGE
Was Detected
Was Detected
APRIL 2006 – Revision 1.1
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / x
1 / x
x / x
1 / x
x / x
x / x
x / x
1 / x
1 / 1
x / x
x / x
Secondary Parity
Secondary Parity
Error Response
Error Response
Primary /
Primary/
PI7C8150A
Bits
Bits