PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 158

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

6
6.1
The FALC
T1/J1 mode.
The device is programmable via a microprocessor interface which enables byte or word
access to all control and status registers.
After reset the FALC
described in sections
Initialization in T1/J1 Mode” on page 163
The status registers are read-only and are updated continuously. Normally, the
processor reads the status registers periodically to analyze the alarm status and
signaling data.
6.2
The FALC
minimum period of 20 µs. During reset the FALC
SCLKR, SCLKX, XTAL1 and XTAL3. All output stages except of CLK16M, CLK12M,
CLK8M, CLKX, FSC, XCLK and RCLK are in a high impedance state, all internal flip-
flops are reset and most of the control registers are initialized with default values.
SIgnals (for example RL1/2 receive line) should not be applied before the device is
powered up.
After reset the device is initialized to E1 operation.
6.3
After reset, the FALC
in the following table.
Table 39
Register
FMR0
FMR1
FMR2
SIC1
SIC2
SIC3
Data Sheet
®
®
Operational Description E1
Operational Overview E1
-LH in principle can be operated in two modes, which are either E1 mode or
Device Reset E1
Device Initialization in E1 Mode
-LH is forced to the reset state if a high signal is input on pin RES for a
Reset Value Meaning
00
00
00
00
00
00
Initial Values after Reset (E1)
H
H
H
H
H
H
®
®
-LH must be initialized first. General guidelines for initialization are
-LH is initialized for doubleframe format with register values listed
“Device Initialization in E1 Mode” on page 158
NRZ coding, no alarm simulation;XL1/2 stay tristate
PCM 30 – doubleframe format, 4.096 Mbit/s system data
rate, no AIS transmission to remote end, payload loop off.
8.192-MHz system clocking rate, receive buffer 2 frames,
transmit buffer bypass, automatic freeze signaling
158
®
-LH needs an active clocks on pins
Operational Description E1
FALC-LH V1.3
and
PEB 2255
“Device
2000-07